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Analog domain adaptive equalizer for low power 40 Gbps DP-QPSK receivers

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Abstract

Electrical domain equalization of chromatic and polarization mode dispersion is attractive in coherent optical communication links. Digital coherent receivers used for this purpose are based on high speed ADCs followed by DSP, which dissipate excessive amount of power and are very costly to implement. We propose analog coherent receiver to drastically reduce the power consumption, size and cost. An adaptive feed forward equalizer for 40 Gbps dual polarization quadrature phase shift keying (DP-QPSK) systems, which processes signals in analog domain itself, is demonstrated using circuit and system simulations. The equalizer, designed in 90 nm CMOS technology, consumes 450 mW of power and occupies 1.8 mm × 1.1 mm chip area. System simulations are used to show that blind equalization is also possible when this approach is used in decision directed mode.

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Acknowledgements

The authors would like to thank Bharti Centre for Communication for providing infrastructure, Indian Institute of Technology Bombay for student support and Department of Science and Technology for funding the project.

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Authors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, 400 076, India

    NANDAKUMAR NAMBATH & SHALABH GUPTA

  2. Sony Corporation, Atsugi, Kanagawa, 243-0014, Japan

    PAWAN KUMAR MOYADE

  3. IBM India Private Limited, Bangalore, 560 076, India

    ALLMIN ANSARI

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  1. NANDAKUMAR NAMBATH
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  2. PAWAN KUMAR MOYADE
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  3. ALLMIN ANSARI
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  4. SHALABH GUPTA
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Correspondence to NANDAKUMAR NAMBATH.

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NAMBATH, N., MOYADE, P.K., ANSARI, A. et al. Analog domain adaptive equalizer for low power 40 Gbps DP-QPSK receivers. Sadhana 39, 409–418 (2014). https://doi.org/10.1007/s12046-013-0218-1

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  • DOI: https://doi.org/10.1007/s12046-013-0218-1

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