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FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time

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Abstract

In this paper, field programmable gate array (FPGA) implementation of reversible watermarking (RW) algorithm by histogram bin shifting (HBS) that can be used for real-time applications of medical and military images has been presented. As the tolerance level of distortion has to be minimal, RW scheme is necessary here. The reversible mode of the process helps in extracting both the original image and the watermark at the receiver end after undergoing through embedding and decoding procedure. The embedded watermark contains the underlying security information of the host images in case of any infringement. Although software implementations of RW schemes are available, very few attempts have been made for hardware realizations of such schemes. The inherent delay associated with software implementations can be minimized by using an on-chip hardware that performs the watermarking process immediately after capturing the image in real time. In this paper, the embedding and decoding procedures involved in the watermarking scheme are implemented using Xilinx System Generator and carries out a detailed design and analysis of the hardware architectures required for the embedding and extraction processes. The device utilization results for both the embedding and decoding process is low and practically viable. The maximum operating frequency for embedding and extraction processes are 445.330 and 201.824 MHz, respectively, which shows improved performance results over similar existing research work in the literature. The power consumptions for embedding and extraction processes are found to be 1.215 and 0.104 W, respectively. To the best of our knowledge, this is the first FPGA-based hardware implementation of RW by HBS.

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Abbreviations

BRAM:

Block random access memory

BUFG:

Global buffer

BUFGCTRL:

Global control buffer

BUFGMUX:

Multiplexed global clock buffer

CPU:

Central processing unit

CT:

Computed tomography

DE:

Difference expansion

ECG:

Electrocardiogram

EPR:

Electronic patient record

FF:

Flip flop

FPGA:

Field programmable gate array

HBS:

Histogram bin shifting

IOB:

Input output block

IRI:

Improved rhombus interpolation

LED:

Light emitting diode

LUT:

Look up table

MRI:

Magnetic resonance imaging

MUX:

Multiplexer

NRE:

Non-recurring engineering

PSNR:

Peak signal-to-noise ratio

P-SoC:

Programmable system-on-chip

RAM:

Random access memory

RCM:

Reversible contrast mapping

RIW:

Reversible image watermarking

ROM:

Read only memory

RW:

Reversible watermarking

WCQ:

Wavelet coefficients quantization

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Acknowledgements

This work has been funded by Special Manpower Development Programme-Chips to System Design (SMDP-C2SD), Department of Electronics and Information Technology (DeitY), Ministry of Communication and Information Technology (MCIT), Government of India.

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Authors and Affiliations

  1. School of VLSI Technology, Indian Institute of Engineering Science and Technology, Shibpur, Howrah, 711103, India

    Sambaran Hazra, Sudip Ghosh & Sayandip De

  2. Department of Information Technology, Indian Institute of Engineering Science and Technology, Shibpur, Howrah, 711103, India

    Hafizur Rahaman

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  1. Sambaran Hazra
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  2. Sudip Ghosh
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  3. Sayandip De
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  4. Hafizur Rahaman
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Correspondence to Sudip Ghosh.

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Hazra, S., Ghosh, S., De, S. et al. FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time. J Real-Time Image Proc 14, 193–221 (2018). https://doi.org/10.1007/s11554-017-0672-9

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  • DOI: https://doi.org/10.1007/s11554-017-0672-9

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