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FPGA implementation of cost-effective robust Canny edge detection algorithm

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Abstract

Implementation of Canny edge detection algorithm significantly outperforms the existing edge detection techniques in many computer vision algorithms. However, Canny edge detection algorithm is complex, time-consuming process with high hardware cost. To overcome these issues, a novel Canny edge detection algorithm is proposed in block level to detect edges without any loss. It uses sobel operator, approximation methods to compute gradient magnitude and orientation for replacing complex operations with reduced hardware cost, existing non-maximum suppression, block classification for adaptive thresholding and existing hysteresis thresholding. Pipelining is introduced to reduce latency. The proposed algorithm is implemented on Xilinx Virtex-5 FPGA and it provides better performance compared to frame-level Canny edge detection algorithm. The synthesized architecture reduces execution time by 6.8 % and utilizes less resource to detect edges of 512 × 512 image compared to existing distributed Canny edge detection algorithm.

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Acknowledgments

The authors are grateful for the financial support provided by Government College of Technology, Coimbatore, Tamil Nadu, India under TEQIP II Scheme.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, Tamil Nadu, 641 013, India

    D. Sangeetha & P. Deepa

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  1. D. Sangeetha
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  2. P. Deepa
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Correspondence to D. Sangeetha.

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Sangeetha, D., Deepa, P. FPGA implementation of cost-effective robust Canny edge detection algorithm. J Real-Time Image Proc 16, 957–970 (2019). https://doi.org/10.1007/s11554-016-0582-2

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