Abstract
On-chip interconnection has posed significant challenges in multiprocessor system on chip (MPSoC) design paradigm, especially in big data era. With respect to the state-of-the-art, crossbar-based interconnection methodologies are still efficient for FPGA-based small-scale heterogeneous MPSoCs. This paper proposes a crossbar-based on-chip interconnection scheme, named CRAIS. CRAIS utilizes reconfigurable crossbar interconnections between microprocessors and intellectual property (IP) cores in MPSoC. The hardware interconnection can be dynamically reconfigured during execution. Empirical results on FPGA prototype demonstrate that CRAIS can achieve more than 7X speedup compared with the state-of-the-art StarNet approach, while it only utilizes 21%∼35% hardware resources of StarNet.
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This work was supported by the National Natural Science Foundation of China under Grant Nos. 61379040, 61272131, 61202053, 61222204, and 61221062, the Natural Science Foundation of Jiangsu Province of China under Grant No. SBK201240198, the Fundamental Research Funds for the Central Universities of China under Grant No. WK0110000034, the Open Project of State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences (CAS) under Grant No. CARCH201407, and the Strategic Priority Research Program of CAS under Grant No. XDA06010403.
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Wang, C., Li, X. & Zhou, XH. CRAIS: A Crossbar-Based Interconnection Scheme on FPGA for Big Data. J. Comput. Sci. Technol. 30, 84–96 (2015). https://doi.org/10.1007/s11390-015-1506-5
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DOI: https://doi.org/10.1007/s11390-015-1506-5