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Design and Power Optimization of High-Speed Pipelined ADC with Programmable Gain Amplifier for Wireless Receiver Applications

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Abstract

This paper proposes a 10-bit 100 MS/s 20 MHz low power pipelined analog-to-digital converter (ADC) with switched capacitor based programmable gain amplifier (PGA) suitable for wireless receiver applications. In the proposed ADC the double loading problem caused in the first stage of 10-bit pipelined ADC is avoided. In order to minimize the power consumption, split-capacitor sharing correlated double sampling and op-amp sharing technique has been used. Using the technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined ADC. Switched capacitor topology based PGA occupies an area of 0.0031 mm2. Switched capacitor topology based PGA with the integration of 10-bit pipelined ADC consumes 25.54 mW of power at 100 MS/s from a 1.8 V power supply.

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Acknowledgments

The authors are grateful to the management of Karunya University for providing necessary facilities in VLSI laboratory to carryout this research work. The authors would like to thank Ms. Anitha, Ms. Neenu for their help in working with the CADENCE software tool.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Karunya University, Coimbatore, Tamil Nadu, 641114, India

    D. S. Shylu & D. Jackuline Moni

  2. Department of Electronics and Communication Engineering, Kathir College of Engineering, Coimbatore, Tamil Nadu, 641062, India

    G. Nivetha

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  1. D. S. Shylu
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  2. D. Jackuline Moni
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  3. G. Nivetha
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Correspondence to D. Jackuline Moni.

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Shylu, D.S., Moni, D. & Nivetha, G. Design and Power Optimization of High-Speed Pipelined ADC with Programmable Gain Amplifier for Wireless Receiver Applications. Wireless Pers Commun 90, 657–678 (2016). https://doi.org/10.1007/s11277-016-3186-z

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