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A Novel Design of Software System on Chip for Embedded System

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Abstract

More and more transistors are integrated onto a single chip. Embedded systems have powerful cores compared with traditional ones. On-chip SRAM is also integrated to provide faster memory access, which is controlled by software and called SPM. In this paper, a novel software system on chip is proposed to take use of SPM. This system consists of microkernel, optimized scheduling module, and the support for multi-programs in parallel. Software system on chip resides in SPM, which can avoid many main memory accesses, improve the performance and reduce the power consumption. Experimental results show that the system can achieve the design goal.

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References

  1. Moore, G.E. (2003). No exponential is forever: but “Forever” can be delayed!. Proceedings of IEEE International Solid-State Circuit Conference, 20–23.

  2. Marwedel, P. (2003). Embedded system design (1st ed.). Dordrecht: Kluwer Academic Publisher.

    MATH  Google Scholar 

  3. Kirsch, C.M., Wilhelm, R. (2007). Grand challenges in embedded software. Proceedings of the 7th ACM&IEEE international conference on Embedded software, 2–6.

  4. Machanick, P. (2002). Approaches to addressing the memory wall. School of IT and Electrical Engineering, University of Queensland.

  5. Wulf, W. A., & Mckee, S. A. (1995). Hitting the memory wall: implications of the obvious[J]. ACM ComputerArchtiecture News, 23(1), 24–29.

    Google Scholar 

  6. Panda, P. R., Catthoor, F., Dutt, N. D., et al. (2001). Data and memory optimization techniques for embedded systems. ACM Transactions on Design Automation of Electronic Systems, 6(2), 149–206.

    Article  Google Scholar 

  7. Benini, L., Macii, A., & Poncino, M. (2003). Energy-aware design of embedded memories: a survey of technologies, architectures, and optimization techniques. ACM Transactions on Embedded Computing Systems, 2(1), 5–32.

    Article  Google Scholar 

  8. Panda, P.R., Dutt, N.D., & Nicolau, A. (1997). Efficient utilization of scratch-pad memory in embedded processor applications. Proceedings of the 1997 European conference on Design and Test, 7–11.

  9. Gabriel, R., Juan T., & Kandemir, M.T. (2014). Volatile STT-RAM scratchpad design and data allocation for low energy. ACM Transactions on Architecture and Code Optimization 11(4), Article 38, 26 p.

  10. Bathen, L. A., Shin, D., Lim, S. S., & Dutt, N. D. (2013). Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution. Design Automation for Embedded Systems, 17(2), 377–409.

    Article  Google Scholar 

  11. Delshadtehrani, L., Farbeh, H., & Miremadi, S.G. (2015). In-scratchpad memory replication: protecting scratchpad memories in multicore embedded systems against soft errors. ACM Transactions on Design Automation of Electronic Systems 20(4), Article 61, 28 p.

  12. Jia, Z.P., Li, Y., Wang, Y., Wang M., & Shao, Z.L. (2015). Temperature-aware data allocation for embedded systems with cache and scratchpad memory. ACM Transactions on Embedded Computing Systems 14(2), Article 30, 24 p.

  13. Absar, J., & Catthoor, F. (2006). Reuse analysis of indirectly indexed arrays. ACM Transactions on Design Automation of Electronic Systems, 11(2), 282–305.

    Article  Google Scholar 

  14. Yang, C. L., Tseng, H. W., Ho, C. C., & Wu, J. L. (2005). Software-controlled cache architecture for energy efficiency. IEEE Transactions on Circuits and Systems for Video Technology, 15(5), 634–644.

    Article  Google Scholar 

  15. Wehmeyer, L., & Marwedel, P. (2005). Influence of memory hierarchies on predictability for time constrained embedded software. Proceedings of Design, Automation and Test in Europe, 2005(1), 600–605.

    Article  Google Scholar 

  16. Angiolini, F., Francesco, M., & Alberto, F., et al. (2004). A post-compiler approach to scratchpad mapping of code. Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, 259–267.

  17. Cooper, K.D., Harvey, T.H. (1998). Compiler-controlled memory. Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, 2–11.

  18. Verma, M., Steinke, S., & Marwedel, P. (2003). Data partitioning for maximal scratchpad usage. Proceedings of the 2003 conference on Asia South Pacific design automation, 77–83.

  19. Steinke, S., Knauer, M., Wehmeyer, L., & Marwedel, P. (2001). An accurate and fine grain instruction-level energy model supporting software optimizations. Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation.

  20. Ozturk, O., Kandemir, M., & Kolcu, I. (2006). Shared scratch-pad memory space management. Preceedings of 7th International Symposium on Quality Electronic Design, 576–584.

  21. Kandemir M., Choudhary A. (2002). Compiler-directed scratch pad memory hierarchy design and management. Proceedings of the 39th conference on Design automation, 628–633.

  22. Ramachandran, A., & Jacome, M. F. (2005). Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(6), 832–848.

    Article  Google Scholar 

  23. Ruggiero, M., Guerri, A., & Bertozzi, D., et al. (2006). Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip. Proceedings of the conference on Design, automation and test in Europe, 3–8.

  24. Scholz, B., Burgstaller, B., & Xue, J.L. (2006). Minimizing bank selection instructions for partitioned memory architecture. Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, 201–211.

  25. Udayakumaran, S., Barua, R. (2003). Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, 276–286.

  26. Udayakumaran, S., Dominguez, A., & Barua, R. (2006). Dynamic allocation for scratch-pad memory using compile-time decisions. Transactions on Embedded Computing Systems, 5(2), 472–511.

    Article  Google Scholar 

  27. Steinke, S., Wehmeyer, L., Lee, B., & Marwedel, P. (2002). Assigning program and data objects to scratchpad for energy reduction. Proceedings of the conference on Design, automation and test in Europe, 409–415.

  28. Chen, T.Z., Zhao, Y., Hu, W., & Xie, B. (2006). Well utilization of cache-aware scratchpad concerning the influence of the whole embedded system. Proceedings of the 2006 IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications, 26–29.

  29. Kandemir, M., Irwin, M.J., Chen, G., & Kolcu, I. (2004). Banked scratch-pad memory management for reducing leakage energy consumption. Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, 120–124.

  30. Hu, W., Chen, T. Z., Shi, Q. S., et al. (2009). A novel operating system on chip with information security support for embedded system. Journal of Software, 4(10), 1053–1060.

    Google Scholar 

  31. Qiu, M. K., Ming, Z., Li, J. Y., et al. (2012). Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors. Journal of Systems Architecture, 58(10), 439–445.

    Article  Google Scholar 

  32. Li, J. Y., Ming, Z., Qiu, M. K., et al. (2011). Resource allocation robustness in multi-core embedded systems with inaccurate information. Journal of Systems Architecture, 57(9), 840–849.

    Article  Google Scholar 

  33. Hu, W., Chen, T. Z., Xie, B., & Yan, L. (2010). Embedded hard real-time scheduling algorithm based on task’s resource requirement. International Journal of High Performance Computing and Networking, 6(3–4), 234–239.

    Article  Google Scholar 

  34. Marvell Corporation. Marvell XScale® PXA27x Processor Family. http://www.marvell.com//application-processors/pxa-family/assets/pxa_27x_pb.pdf.

  35. Hu, W., Chen, T.Z., Xie, B., & Shi, Q.S. (2006). Embedded real-time linux on chip: Next generation operation system for embedded system. Proceedings of Eighth Real-Time Linux Workshop, 167–172.

  36. Guthaus, M.R., et al. (2001). Mibench: A free, commercially representative embedded benchmark suite. Proceedings of IEEE Annual Workshop on Workload Characterization, 3–14.

  37. Lee, C., Potkonjak, M., & Manione-Smith, W.H. (1997). Mediabench: A tool for evaluating multimedia and communications systems. Proceedings of 30th Annu. IEEE Conf. Microarchitecture, 330–335.

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Acknowledgments

This work was supported by National Natural Science Foundation of China (Granted No. 61100055 and 61403287).

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Authors and Affiliations

  1. College of Computer Science and Technology, Wuhan University of Science and Technology, Wuhan, Hubei, 430065, China

    Wei Hu, Hong Guo, Hongna Geng, Kai Zhang, Jun Liu & Xiaoming Liu

  2. Hubei Province Key Laboratory of Intelligent Information Processing and Real-time Industrial System, Wuhan, Hubei, 430065, China

    Wei Hu, Hong Guo, Hongna Geng, Kai Zhang, Jun Liu & Xiaoming Liu

Authors
  1. Wei Hu
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  2. Hong Guo
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  3. Hongna Geng
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Correspondence to Hong Guo.

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Hu, W., Guo, H., Geng, H. et al. A Novel Design of Software System on Chip for Embedded System. J Sign Process Syst 86, 135–147 (2017). https://doi.org/10.1007/s11265-015-1099-9

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  • DOI: https://doi.org/10.1007/s11265-015-1099-9

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