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Framework for Digital Filter Design Optimization (DiFiDOT) using MCM Based Register Minimization Retiming for Noise Removal ECG Filters

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Abstract

In all the DSP(Digital Signal Processing) blocks such as digital filters, the filter coefficients are known before hand. Hence, full flexibility of the multiplier is not necessary. Multiplierless Multiple Constant Multiplication(MCM) technique can be used along with retiming for better digital filter optimization.This method is more efficient when compared to shift and add multiplications as intermediate results in MCM technique can be shared which reduces the area of multiplierless implementation of digital filters. The multiplierless filter circuit is further retimed to reduce the overall clock period which increases the clock frequency. Critical path and shortest path computations consume most of the time in retiming computation. The retiming minimizes the overall clock period by reducing the filter critical path. In the general purpose processor where actual retiming vectors are computed for digital filters, the speed with which the retiming transformation is performed suffers as the entire transformation code will be written in the form of a soft core. Hence, FPGA based path solver architecture are proposed in this paper can reduces the burden on general purpose processors while retiming. This work contributes to reduced processing time for retiming using FPGA based path solvers. Due to complexity and transistor size reduction, designing of VLSI architectures for DSP blocks has become very challenging. Automated Tools are required most often to introduce the products to market in a timely manner and to make the VLSI designs more stable, reliable and tractable. A framework called DiFiDOT(Digital Filter Design Optimization Tool) is developed in this work for synthesizing the optimized filter architectures. Finally, an application for Electrocardiography(ECG) is designed using MCM based retimed digital filters to remove the power supply interference, baseline drift and the broadband noise from the ECG signal.

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References

  1. Leiserson, C. E., Rose, F. M., & Saxe, J.B. (1983). Optimizing synchronous circuitry by retiming (preliminary version). In Third Caltech conference on very large scale integration (pp. 87–116). Springer.

  2. Dey, S., Potkonjak, M., & Rothweiler, S. G. (1992). Performance optimization of sequential circuits by eliminating retiming bottlenecks. In 1992 IEEE/ACM international conference on computer-aided design, 1992. ICCAD-92. Digest of technical papers (pp. 504–509). IEEE.

  3. Simon, S., Bernard, E., Sauer, M., & Nossek, J. A. (1994). A new retiming algorithm for circuit design. In 1994 IEEE international symposium on circuits and systems, 1994. ISCAS’94 (Vol. 4, pp. 35–38). IEEE.

  4. Maheshwari, N., & Sapatnekar, S. (1998). Efficient retiming of large circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(1), 74–83.

    Article  Google Scholar 

  5. Chakradhar, S. T., & Dey, S. (1999). Resynthesis and retiming for optimum partial scan. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(5), 621–630.

    Article  Google Scholar 

  6. Yagain, Deepa, & Vijayakrishna, A. (2015). A novel framework for retiming using evolutionary computation for high level synthesis of digital filters. Swarm and Evolutionary Computation, 20, 37–47.

    Article  Google Scholar 

  7. El-Maleh, A. H., & Osais, Y. E. (2001). A retiming-based test pattern generator design for built-in self test of data path architectures. In The 2001 IEEE international symposium on circuits and systems, 2001. ISCAS 2001 (Vol. 4, pp. 550–553). IEEE.

  8. Tabbara, A., Tabbara, B., Brayton, R. K., & Newton, A. R. (2000). Integration of retiming with architectural floorplanning. The VLSI Journal of Integration, 29(1), 25–43.

    Article  MATH  Google Scholar 

  9. Young, C., & Jones, D. L. (1991). Area-efficient vlsi implementation of fir digital filters using shifted partial products. In Conference record of the twenty-fifth Asilomar conference on signals, systems and computers, 1991 (pp. 398–402). IEEE.

  10. Bull, D., & Horrocks, D. (1991). Primitive operator digital filters. IEE Proceedings G (Circuits, Devices and Systems), 138(3), 401–412.

    Article  Google Scholar 

  11. Dempster, A. G., & Macleod, M. D. (1995). Use of minimum-adder multiplier blocks in fir digital filters. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42(9), 569–577.

    Article  MATH  Google Scholar 

  12. Hartley, R. I. (1996). Subexpression sharing in filters using canonic signed digit multipliers. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 43(10), 677–688.

    Article  Google Scholar 

  13. Pasko, R., Schaumont, P., Derudder, V., Vernalde, S., & Durackova, D. (1999). A new algorithm for elimination of common subexpressions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(1), 58–68.

    Article  Google Scholar 

  14. Yurdakul, A., & Dündar, G. (1999). Multiplierless realization of linear dsp transforms by using common two-term expressions. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 22(3), 163–172.

    Article  Google Scholar 

  15. Dempster, A. G., & Macleod, M. D. (1994). Constant integer multiplication using minimum adders. Devices and Systems of IEEE Proceedings-Circuits, 141(5), 407–413.

    Article  MATH  Google Scholar 

  16. Flores, P., Monteiro, J., & Costa, E (2005). An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. In IEEE/ACM international conference on computer-aided design, 2005. ICCAD-2005 (pp. 13–16). IEEE.

  17. Aksoy, L., Costa, E., Flores, P., & Monteiro, J. (2006). Optimization of area under a delay constraint in digital filter synthesis using sat-based integer linear programming. In Proceedings of the 43rd annual design automation conference (pp. 669–674). ACM.

  18. Passos, N. L., Sha, E.-M., & Bass, S. C. (1996). Optimizing dsp flow graphs via schedule-based multidimensional retiming. IEEE Transactions on Signal Processing, 44(1), 150–155.

    Article  Google Scholar 

  19. Yagain, D., & Krishna, A V (2014). Design of synthesizable, retimed digital filters using FPGA based path solvers with MCM approach: comparison and CAD tool. In VLSI design journal (Vol. 2014). Hindawi Publishing Corp.

  20. Aksoy, L., Da Costa, E., Flores, P., & Monteiro, J. (2008). Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 27(6), 1013–1026.

    Article  Google Scholar 

  21. Ho, Y.-H. A., Lei, C.-U., Kwan, H.-K., & Wong, N. (2008). Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications. In Proceedings of the 2008 Asia and South Pacific design automation conference (pp. 119–124). IEEE Computer Society Press.

  22. Aksoy, L., Gunes, E. O., & Flores, P. (2008). An exact breadth-first search algorithm for the multiple constant multiplications problem. In NORCHIP, 2008 (pp. 41–46). IEEE.

  23. Voronenko, Y., & Püschel, M. (2007). Multiplierless multiple constant multiplication. ACM Transactions on Algorithms (TALG), 3(2), 11.

    Article  MathSciNet  MATH  Google Scholar 

  24. Cong, J., Liu, B., Neuendorffer, S., Noguera, J., Vissers, K., & Zhang, Z. (2011). High-level synthesis for fpgas: from prototyping to deployment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(4), 473–491.

    Article  Google Scholar 

  25. Cornu, A., Derrien, S., & Lavenier, D (2011). Hls tools for fpga: faster development with better performance. In Reconfigurable computing: architectures, tools and applications (pp. 67–78). Springer.

  26. Yagain, D, Balla, S., Krishna, V., Balla, S., & Krishna, V. (2015). Efficient audio filter using folded pipelining architecture based on retiming using evolutionary computation. In Journal of circuits, systems and computers (pp. 1550068). World Scientific.

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Acknowledgments

We would like to acknowledge with much appreciation the support and help of S N S SRI HARSHA ARADHYA, MTech Student, Department of ECE, PES Institute of Technology, Bangalore for his contribution towards the completion of this research work.

Conflict of interest

Deepa Yagain and Dr.Vijayakrishna A. state that there are no conflicts of interest.

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  1. Department of ECE, PESIT, Bangalore, India

    Deepa Yagain & VijayaKrishna A

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  1. Deepa Yagain
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  2. VijayaKrishna A
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Correspondence to Deepa Yagain.

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Yagain, D., A, V. Framework for Digital Filter Design Optimization (DiFiDOT) using MCM Based Register Minimization Retiming for Noise Removal ECG Filters. J Sign Process Syst 84, 197–210 (2016). https://doi.org/10.1007/s11265-015-1037-x

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  • DOI: https://doi.org/10.1007/s11265-015-1037-x

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