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Multi-core DSP-based Vector Set Bits Counters/Comparators

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Abstract

The paper shows that fast counting non-zero components (Hamming weights) and comparing the results (Hamming distances) in large sets of data items is important for numerous practical applications and this problem has been broadly investigated by software and hardware designers. It is frequently referenced as population or vector set bits count (or simply popcount). This paper is dedicated to multi-core FPGA-based accelerators that compute Hamming weights/distances and compare the results with fixed thresholds and variable bounds. It is shown that widely available in contemporary FPGAs digital signal processing slices may be used efficiently and they provide the fastest and the less resource consuming solutions. A thorough analysis and comparison with the best known alternatives both in hardware and in software is presented and supported by numerous experiments in the recent Nexys-4, ZedBoard and ZyBo prototyping systems. Complete hardware description language (VHDL) specifications for core components are given ready to be synthesized, implemented, tested and evaluated. Experiments with the proposed designs clearly demonstrate significant speed-up comparing to known hardware/software alternatives.

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Authors and Affiliations

  1. Department of Electronics, Telecommunications and Informatics, IEETA, University of Aveiro, 3810-193, Aveiro, Portugal

    Valery Sklyarov & Iouliia Skliarova

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  1. Valery Sklyarov
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  2. Iouliia Skliarova
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Correspondence to Iouliia Skliarova.

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Sklyarov, V., Skliarova, I. Multi-core DSP-based Vector Set Bits Counters/Comparators. J Sign Process Syst 80, 309–322 (2015). https://doi.org/10.1007/s11265-014-0915-y

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  • DOI: https://doi.org/10.1007/s11265-014-0915-y

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