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Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction

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Abstract

Multiple dynamic supply voltage (MDSV) designs can be used to reduce power consumption. However, power modes operation with different voltages will cause increasing of the clock skew. The adjustable delay buffers (ADBs) can be used to minimize clock skew under different power modes but it is unlikely to add an unlimited number of ADBs in real world. In the paper, we first assign positions of adjustable delay buffers in a given clock tree to generate zero clock skew. If the number of ADBs is not satisfied with the constraints in the previous solution, a bottom-up method is then used to remove some adjustable delay buffers so that the clock skew is minimized under satisfying all constraints. Finally, the experimental results show that our design is very practical.

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Acknowledgments

This work was supported by National Science Council, Taiwan NSC 101-2221-E-024-020.

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  1. Department of Computer Science and Information Engineering, National University of Tainan, Tainan, Taiwan

    Chi-Chou Kao

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  1. Chi-Chou Kao
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Correspondence to Chi-Chou Kao.

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Kao, CC. Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction. J Sign Process Syst 79, 99–104 (2015). https://doi.org/10.1007/s11265-014-0888-x

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  • DOI: https://doi.org/10.1007/s11265-014-0888-x

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