Total Power Optimization for Combinational Logic Using Genetic Algorithms
Purchase on Springer.com
$39.95 / €34.95 / £29.95*
Rent the article at a discountRent now
* Final gross prices may vary according to local VAT.
Power consumption is a top priority in high performance circuit design today. Many low power techniques have been proposed to tackle the ever serious, highly pressing power consumption problem, which is composed of both dynamic and static power in the nanometer era. The static power consumption nowadays receives even more attention than that of dynamic power consumption when technology scales below 100 nm. In order to mitigate the aggressive power consumption, various existing low power techniques are often used; however, they are often applied independently or combined with two or at most three different techniques together, and that is not sufficient to address the escalating power issue. In this paper, we present a power optimization framework for the minimization of total power consumption in combinational logic through multiple V dd assignment, multiple V th assignment, device sizing, and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded into the genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are presented for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier, and a 32 bit carry adder. Our experiments show that the combination of four low power techniques is the effective way to achieve low power budget. The framework is general and can be easily extended to include other design-time low power techniques, such as multiple gate length or multiple gate oxide thickness.
- Usami, K., & Horowitz, M. (1995). Clustered voltage scaling techniques for low-power design. In Proceedings of the International Symposium on Low power design (pp. 3–8).
- Wang, Q., & Vrudhula, S. (2002). Algorithms for minimizing standby power in deep submicron, dual-Vt CMOS circuits. IEEE Transactions on Computer-Aided Design, 21, 306–318. CrossRef
- Puri, R., Stok, L., Cohn, J., Kung, D., Pan, D., Sylvester, D., et al. (2003). Pushing ASIC performance in a power envelope. In Proceedings of Design Automation Conference (pp. 788–793).
- Rabaey, J., Chandrakasan, A., & Nikolic, B. (2003). Digital integrated circuits: A design perspective. Second edition. NJ: Prentice Hall.
- Hamada, M., & Ootaguro, Y. (2001). Utilizing surplus timing for power reduction. In Proceedings of the IEEE Custom Integrated Circuits Conference (pp. 89–92).
- Brodersen, R., Horowitz, M., Markovic, D., Nikolic, B., & Stojanovic, V. (2002). Methods for true power minimization. In Proceedings of Computer-Aided Design (pp. 35–42).
- Narendra, S., Borkar, S., De, V., Antoniadis, D., & Chandrakasan, A. (2001). Scaling of stack effect and its application for leakage reduction. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 195–200).
- Stojanovic, V., Markovic, D., Nikolic, B., Horowitz, M., & Brodersen, R. (2002). Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization. In Proceedings of European Solid-State Circuits Conference (pp. 211–214).
- Roy, K., Wei, L., & Chen, Z. (1999). Multiple Vdd Multiple Vth (MVCMOS) for lower power applications. International Symposium on Circuits and Systems (pp. 366–370).
- Augsburger, S., & Nikolic, B. (2002). Reducing power with dual supply, dual threshold and transistor sizing. International Conference on Computer Design (pp. 316–321).
- Sirichotiyakul, S., Edwards, T., Oh, C., Zuo, J., Dharchoudhury, A., Panda, R., et al. (1999). Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing. In Proceedings of Design Automation Conference (pp. 436–441).
- Karnik, T., Ye, Y., Tschanz, J., Wei, L., Burns, S., Govindarajulu, V., et al. (2002). Total power optimization by simultaneous Dual-Vt allocation and device sizing in high performance microprocessors. In Proceedings of Design Automation Conference (pp. 486–491).
- Srivastava, A., & Sylvester, D. (2003). Minimizing total power by simultaneous Vdd/Vth assignment. In Proceedings of Asia-South Pacific Design Automation Conference (pp. 400–403).
- Nguyen, D., Davare, A., Orshansky, M., Chinnery, D., Thompson, B., & Keutzer, K. (2003). Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 158–163).
- Goldberg, D. E. (1989). Genetic algorithms in search, optimization, and machine learning. New York: Addison-Wesley.
- Sutherland, I. V., Sproull, R. F. & Harris, D. F. (1999). Logical effort, M. Kaufmann.
- http://www.device.eecs.berkeley.edu, Berkeley predictive model.
- Schaffer, J., Caruana, J., Eshelman, L., & Das, R. (1989). A study of control parameters affecting online performance of genetic algorithms for function optimization. In Proceedings of International Conference on Genetic Algorithms (pp. 51–60).
- Lee, D., Deogun, H., Blaauw, D., & Sylvester, D. (2004). Simultaneous state, Vt and Tox assignment for total standby power minimization. In Proceedings of Design, Automation and Test in Europe (pp. 494–499).
- Srivastava, A., Sylvester, D., & Blaauw, D. (2004). Concurrent sizing, Vdd and Vth assignment for low-power design. In Proceedings of Design, Automation and Test in Europe (pp. 718–719).
- Hung, W., Xie, Y., Vijaykrishnan, N., Kandemire, M., Irwin, M. J., & Tsai, Y. (2004). Total power optimization through simultaneously Multiple-VDD, Multiple-VTH assignment and device sizing with stack forcing. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 144–149).
- Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanzawa, M., Ichida, M., et al. (1997). Automated low-power techniques exploiting multiple supply voltage applied to a media processor. In Proceedings of Custom Integrated Circuits Conference (pp. 131–134).
- Saab, Y. G., & Rao, V. B. (1989). An evolution-based approach to partitioning ASIC systems. In Proceedings of Design Automation Conference (pp. 767–770).
- Cohoon, J. P., & Paris, W. (1996). Genetic placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 6(6), 956–964. CrossRef
- Chan, H., Mazumder, P., & Shahookar, K. (1991). Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome. Integration: The VLSI Journal, 12(1), 49–77. CrossRef
- Bright, M. S., & Arslan, T. (1996). A genetic framework for the high-level optimization of low power VLSI DSP systems. IEEE Electron Letters, 32(13), 1150–1151. CrossRef
- Lobo, F. G., Goldberg, D. E., & Pelikan, M. (2000). Time complexity of genetic algorithms on exponentially scaled problems. In Proceedings of the Genetic and Evolutionary Computation Conference.
- Chinnery, D. G., & Keutzer, K. (2005). Linear programming for sizing, Vth and Vdd assignment. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 149–154).
- Ekpanyapong, M., & Lim, S. K. (2006). Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization. In ACM International Symposium on Physical Design (pp. 142–148).
- Diril, A., Dhillon, Y., Chatterjee, A., & Singh, A. (2005). Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13(9), 1103–1107. CrossRef
- Srivastava, A., & Sylvester, D. (2004). Minimizing total power by simultaneous Vdd/Vth assignments. In Proceedings of the Asia and South Pacific Design Automation Conference (pp. 400–403).
- Ghavami, B., Khosraviani, M., & Pedram, H. (2008). Power optimization of asynchronous circuits through simultaneous Vdd and Vth assignment and template sizing. In Proceedings of the 11th EUROMICRO conference on Digital System Design Architectures, Methods and Tools (pp. 274–281).
- Ouyang, J., & Xie, Y. (2008). Power optimization for FinFET-based circuits using genetic algorithms. In Proceedings of IEEE International SOC Conference (pp. 211–214).
- Chi, J., Lee, H., Tsai, S., & Chi, M. (2007). Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(6), 637–648. CrossRef
- Morifuji, E., Patil, D., Horowitz, M., & Nishi, Y. (2007). Power Q2 optimization for SRAM and its scaling. IEEE Transactions on Electron Devices, 54(4), 715–722. CrossRef
- Dabiri, F., Nahapetian, A., Massey, T., Potkonjak, M., & Sarrafzadeh, M. (2008). General methodology for soft-error-aware power optimization using gate sizing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(10), 1788–1797. CrossRef
- Dutta, S., Nag, S., & Roy, K. (1994). ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits. In Proceedings of IEEE International Symposium on Circuits and Systems (pp. 61–64).
- Total Power Optimization for Combinational Logic Using Genetic Algorithms
Journal of Signal Processing Systems
Volume 58, Issue 2 , pp 145-160
- Cover Date
- Print ISSN
- Online ISSN
- Springer US
- Additional Links
- Power optimization
- Genetic algorithm
- VLSI circuits
- Industry Sectors