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Static probabilistic timing analysis for real-time systems using random replacement caches

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Abstract

In this paper, we investigate static probabilistic timing analysis (SPTA) for single processor real-time systems that use a cache with an evict-on-miss random replacement policy. We show that previously published formulae for the probability of a cache hit can produce results that are optimistic and unsound when used to compute probabilistic worst-case execution time (pWCET) distributions. We investigate the correctness, optimality, and precision of different approaches to SPTA for random replacement caches. We prove that one of the previously published formulae for the probability of a cache hit is optimal with respect to the limited information (reuse distance and cache associativity) that it uses. We derive an alternative formulation that makes use of additional information in the form of the number of distinct memory blocks accessed (the stack distance). This provides a complementary lower bound that can be used together with previously published formula to obtain more accurate analysis. We improve upon this joint approach by using extra information about cache contention. To investigate the precision of various approaches to SPTA, we introduce a simple exhaustive method that computes a precise pWCET distribution, albeit at the cost of exponential complexity. We integrate this precise approach, applied to small numbers of frequently accessed memory blocks, with imprecise analysis of other memory blocks, to form a combined approach that improves precision, without significantly increasing complexity. The performance of the various approaches are compared on benchmark programs. We also make comparisons against deterministic analysis of the least recently used replacement policy.

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Notes

  1. In a fully associative cache, any memory block may be placed in any cache line.

  2. The term stack distance of an element \(e_l\) refers to the position of the element on a stack with least-recently used ordering.

  3. Each memory access with a stack distance larger than or equal to the associativity results in a cache miss in the case of an LRU cache, while each memory access with a smaller stack distance results in a cache hit.

  4. http://pp.ipd.kit.edu/firm/Index

  5. http://www.arm.com/products/processors/classic/arm7

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Acknowledgments

This work was partially funded by COST Action IC1202: Timing Analysis On Code-Level (TACLe), the UK EPSRC Project MCC (EP/K011626/1), and the EU FP7 Integrated Project PROXIMA (611085).

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Altmeyer, S., Cucu-Grosjean, L. & Davis, R.I. Static probabilistic timing analysis for real-time systems using random replacement caches. Real-Time Syst 51, 77–123 (2015). https://doi.org/10.1007/s11241-014-9218-4

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