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Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems

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Abstract

Photonic networks-on-chip (PNoCs) promise significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In conventional hybrid-PNoC systems, several electrical control functions, such as path setup, acknowledgment and Tear-down are necessary for the end-to-end optical transfer. However, the circuit-switched nature of photonic interconnect directly affects the performance and power characteristics of on-chip communication. In this paper, we propose an energy-efficient and high-throughput hybrid silicon-photonic network-on-chip, named PHENIC, targeted for future generations of high-performance many-core systems. PHENIC is based on a smart contention-aware path-configuration algorithm and an energy-efficient non-blocking optical switch to further exploit the low energy proprieties of the PNoC systems. Through detailed simulation, we demonstrate that the proposed system has a better performance and low energy dissipation compared to conventional hybrid-PNoCs.

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Acknowledgments

This work is partially supported by the University of Aizu Competitive Research Funding (CRF), Ref. P-12-2014-2015. We wish to thank all anonymous reviewers for providing us useful comments and suggestions.

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Correspondence to Achraf Ben Ahmed.

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PHENIC project is supported by University of Aizu Competitive Research Funding, Ref. P-12-2014-2015.

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Ben Ahmed, A., Ben Abdallah, A. Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems. J Supercomput 71, 4446–4475 (2015). https://doi.org/10.1007/s11227-015-1539-0

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