Skip to main content

Advertisement

SpringerLink
Log in

Master-based routing algorithm and communication-based cluster topology for 2D NoC

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

As size of chip is becoming smaller with growth in technology, and due to increase in number of cores, system-on-chip (SoC) becomes very complex. Network-on-chip (NoC) provides best solution to SoC by reducing communication overhead. The basic concern of NoC is the speed, performance and accuracy along with the small size of chip. The existing NoC topologies such as mesh topology, bus topology, torus topology, fat tree topology does not provide optimized performance. In this paper, we have proposed communication-based cluster topology (CBCT), which is based on 2H, i.e., heterogeneous and hybrid, proves to be more efficient topology by providing better performance due to reduction in latency, link utilization and energy consumption involved during communication. In experimental result, CBCT approach is compared with 2D mesh topology and CBCT proves to provide better results in terms of an end-to-end latency, network latency, packet latency, sink bandwidth, loss probability, link utilization and energy consumption of a topology.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. Agarwal M, Dubey R, Jain N, Raghuvanshi D (2013) Comparative analysis of different topologies based on network-on-chip architectures. Int J Electron Commun Eng 6:29–40

    Google Scholar 

  2. Owens JD, Dally WJ, Ho R, Jayasimha DNJ, Keckler SW, Peh L-S (2007) Research challenges for on-chip interconnection networks. IEEE Micro 5:96–108

    Article  Google Scholar 

  3. Sehgal V (2014) Markovian models based stochastic communication in networks-in-package. IEEE Trans Parallel Distrib Syst 26(10):2806–2821

    Article  Google Scholar 

  4. Ingle VV, Gaikwad MA (2013) Mesh topology of NoC architecture using source routing algorithm. Int J Eng Adv Technol (IJEAT) 2:101–104

    Google Scholar 

  5. Benini L, De Micheli G (2002) Networks on chip: a new SoC paradigm. IEEE Comput 31(1):7078

    Google Scholar 

  6. Pavlidis VF, Friedman EG (2007) 3-D topologies for networks-on-chip. IEEE transactions on very large scale integration (VLSI) systems 15:1081–1090

    Article  Google Scholar 

  7. Choudhary N (2012) Network-on-chip: a new SoC communication infrastructure paradigm. Int J Soft Comput Eng (IJSCE) 1:332–335

    Google Scholar 

  8. Sehgal VK, Chauhan DS (2010) State observer controller design for packets flow control in networks-on-chip. J Supercomput 54(3):298–329

    Article  Google Scholar 

  9. Benini L, De Micheli G (2002) Energy-efficient system-level design, Springer book power aware design methodologies, chapter 16. Springer, New York

    Google Scholar 

  10. Bertozzi D, Benini L, De Micheli G (2004) Energy-efficient network-on-chip design. In: Macii E (ed) Ultra low-power electronics and design. Kluwer, Dordrecht, pp 214–232

  11. Marculescu R, Ogras UY, Peh L-S, Jerger NE, Hoskote Y (2009) Outstanding research problems in NoC design: circuit-, microarchitecture-, and system-level perspectives. IEEE Trans Comput Aided Des Integr Circuits Syst 28:3–21

    Article  Google Scholar 

  12. Chen J, Li C, Gillard P (2011) Network-on-Chip (NoC) topologies and performance: a review. In: Proceedings of the 2011 Newfoundland Electrical and Computer Engineering Conference (NECEC), pp 1–6

  13. Baboli M, Husin NS, Marsono MN (2014) A comprehensive evaluation of direct and indirect network-on-chip topologies. In: Proceedings of the 2014 international conference on industrial engineering and operations management, pp 2081–2090

  14. Patel S, Parandkar P, Katiyal S, Agrawal A (2011) Exploring alternative topologies for network-on-chip architectures. Int J Inf Technol 3:372–376

    Google Scholar 

  15. Abou El Hassan BENYAMINA, Pierre BOULET (2007) Multi-objective mapping for NoC architectures. J Digit Inf Manag 5:378–384

    Google Scholar 

  16. Choudhary N (2013) Migration of on-chip networks from 2 dimensional plane to 3 dimensional plane. Int J Eng Adv Technol 2:516–519

    Google Scholar 

  17. Duato J, Yalamanchili S, Ni L (2003) Interconnection networks: an engineering approach. Elsevier, Amsterdam 2003

    Google Scholar 

  18. Xu Y, Zhou J, Liu S (2011) Research and analysis of routing algorithms for NoC, 3rd international conference on computer research and development (ICCRD), pp 98–102

  19. Ingle VV, Gaikwad MA (2013) Review of mesh topology of NoC architecture using source routing algorithms. Int J Comput Appl 4:30–34

    Google Scholar 

  20. Chawade SD, Gaikwad MA, Patrikar RM (2006) Design XY routing algorithm for network-on-chip architecture. Int J Res Dev 1(1):1–5

    Google Scholar 

  21. Rohini A (2013) Design and implementation of minimal adaptive west first algorithm for NoC router architecture. In: Proceedings of the 2013 National Conference on ‘Women in Science & Engineering’ (NCWSE), pp 269–273

  22. Hansson A, Goossens K, Radulescu A (2007) Avoiding message-dependent deadlock in network-based systems on chip, VLSI design. Hindawi publishing corporation, Cairo

    Google Scholar 

  23. Bhandarkar SM, Arabnia HR (1995) The REFINE multiprocessor—theoretical properties and algorithms. Parallel Comput 21(11):1783–1805

    Article  Google Scholar 

  24. Bhandarkar SM, Arabnia HR (1995) The hough transform on a reconfigurable multi-ring network. J Parallel Distrib Comput 24(1):107–114

    Article  Google Scholar 

  25. Bhandarkar SM, Arabnia HR, Smith JW (1995) A reconfigurable architecture for image processing and computer vision. Int J Pattern Recognit Artif Intell (IJPRAI) 9(2):201–229 (special issue on VLSI Algorithms and Architectures for Computer Vision, Image Processing, Pattern Recognition And AI)

    Article  Google Scholar 

  26. Arabnia HR, Bhandarkar SM (1996) Parallel stereocorrelation on a reconfigurable multi-ring network. J Supercomput 10(3):243–270

    Article  MATH  Google Scholar 

  27. Arif Wani M, Arabnia HR (2003) Parallel edge-region-based segmentation algorithm targeted at reconfigurable multi-ring network. J Supercomput 25(1):43–63

    Article  MATH  Google Scholar 

  28. Chan J, Parameswaran S (2008) NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. In: Proceedings of the 2008 Asia and South Pacific design automation conference, pp 265–270

  29. Li C-L, Lee JH, Yang J-S, Han TH (2014) Communication-aware custom topology generation for VFI network-on-chip. IEICE Electron Express 11:1–8

    Google Scholar 

  30. Ge F, Wu N, Qin X, Zhang Y (2011) Clustering-based topology generation approach for application-specific network on chip. In: Proceedings of the world congress on engineering and computer science, vol 2 (2011)

  31. Jain S, Choudhary N, Singh D (2014) STG-NoC: a tool for generating energy optimized custom built NoC topology. Int J Comput Appl 15:22–26

    Google Scholar 

  32. Srinivasan K, Chatha KS, Konjevod G (2005) An automated technique for topology and route generation of application specific on-chip interconnection networks. In: IEEE/ACM international conference on computer-aided design, pp 231–237

  33. Dafali R, Diguet J-P (2010) MPSoC architecture-aware automatic NoC topology design. Netw Parallel Comput 6289:470–480

    Article  Google Scholar 

  34. Choudhary N, Gaur MS, Laxmi V (2011) Energy efficient network generation for application specific NoC. Glob J Comput Sci Technol 11(16):47–56

    Google Scholar 

  35. Tino A, Khan GN (2011) Multi-Objective tabu search based topology generation technique for application-specific network-on-chip architectures. In: Design, automation & test in Europe conference & exhibition (DATE), pp 1–6

  36. Vellanki P, Banerjee N, Chatha KS (2004) Quality-of-service and error control techniques for network-on-chip architectures. In: Proceedings of the 14th ACM great lakes symposium on VLSI, pp 45–50

  37. Zhanga N, Huaxi G, Yang Y, Fan D (2014) QBNoC: QoS-aware bufferless NoC architecture. Microelectron J 45(6):751–758

    Article  Google Scholar 

  38. Li B, Zhaoa L, Iyer R, Peh L-S, Leddige M, Espig M, Lee SE, Newell D (2010) CoQoS: coordinating QoS-aware shared resources in NoC-based SoCs. J Parallel Distrib Comput 71(5):700–713

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, Jaypee University of Information Technology, Solan, India

    Suchi Johari & Vivek Kumar Sehgal

Authors
  1. Suchi Johari
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Vivek Kumar Sehgal
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Vivek Kumar Sehgal.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Johari, S., Sehgal, V.K. Master-based routing algorithm and communication-based cluster topology for 2D NoC. J Supercomput 71, 4260–4286 (2015). https://doi.org/10.1007/s11227-015-1521-x

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-015-1521-x

Keywords

Search

Navigation