Skip to main content
SpringerLink
Log in

Improving fault-tolerance capability of on-chip binary CDMA bus

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

Shrinking technology and growing complexity of the contemporary system on chip designs require high performance and reliable interconnection architecture. Binary CDMA on-chip bus permits simultaneous use of the shared communication medium by multiple data streams and alleviates contention and queuing delays experienced by a conventional time-division multiplexing shared bus. In this paper, we present an encoding scheme for improving reliability of the on-chip interconnect system based on a binary CDMA bus. Without adding extra wires to the bus, the proposed encoding method replaces the standard binary encoding with a non-weighted code which tolerates single-bit error at any bus wire within the timing window of a single CDMA transaction. In addition, we derive constraints for a codeword selection under which the single-bit error tolerance is achieved and provide a recursive algorithm for code construction. Simulation results show that the proposed encoding scheme significantly improves the post-decoding bit error rate performance of the binary CDMA bus under a binary symmetric channel model.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

References

  1. Chiang MC, Sohi GS (1992) Evaluating design choices for shared Bus multiprocessors in a throughput-oriented environment. IEEE Trans Comput 41(3):297–317. doi:10.1109/12.127442

    Article  Google Scholar 

  2. Kim J, Lai BC, Chang M-CF, Verbauwhede I (2008) A cost-effective latency-aware memory bus for symmetric multiprocessor systems. IEEE Trans Comput 57(12):1714–1719. doi:10.1109/TC.2008.96

    Article  MathSciNet  Google Scholar 

  3. Kim J, Verbauwhede I, Chang M-CF (2007) Design of an interconnect architecture and signaling technology for parallelism in communication. IEEE Trans Very Large Scale Integr Syst 15(8):881–894. doi:10.1109/TVLSI.2007.900739

    Article  Google Scholar 

  4. Chang M-CF, Verbauwhede I, Chien C, Xu Z (2005) Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications. IEEE Trans Electron Devices 52(7):1271–1285. doi:10.1109/TED.2005.850699

    Article  Google Scholar 

  5. Pasricha S, Dutt N (2008) On-chip communication architectures: system on chip interconnect. Elsevier, Morgan Kauffman, Amsterdam

    Google Scholar 

  6. Wani MA, Arabnia HR (2003) Parallel edge-region-based segmentation algorithm targeted at reconfigurable multi-ring network. J Supercomput 25(1):43–63. doi:10.1023/A:1022804606389

    Article  MATH  Google Scholar 

  7. Bhandarkar SM, Arabnia HR (1995) The hough transform on a reconfigurable multi-ring network. J Parallel Distrib Comput 24(1):107–114. doi:10.1006/jpdc.1995.1011

    Article  Google Scholar 

  8. Arabnia HR, Bhandarkar SM (1996) Parallel stereocorrelation on a reconfigurable multi-ring network. J Supercomput 10(3):243–270. doi:10.1007/BF00130109

    Article  MATH  Google Scholar 

  9. Raghunathan V, Srivastava MB, Gupta RK (2003) A survey of techniques for energy efficient on chip communication. In: Proceedings design automation conference, pp 900–905. doi:10.1109/DAC.2003.1219148

  10. Halak B, Ma T, Wei X (2014) A dynamic CDMA network for multicore systems. Microelectron J 45(4):424–434. doi:10.1016/j.mejo.2014.02.002

    Article  Google Scholar 

  11. Kim M, Kim D, Sobelman GE (2005) Adaptive scheduling for CDMA-based networks-on-chip. In: The 3rd international IEEE-NEWCAS conference, pp 357–360. doi:10.1109/NEWCAS.2005.1496682

  12. Wang X, Ahonen T, Nurmi J (2007) Applying CDMA technique to network-on-chip. IEEE Trans Very Large Scale Integr Syst 15(10):1091–1100. doi:10.1109/TVLSI.2007.903914

    Article  Google Scholar 

  13. Bell Jr RH, Chang KY, John L, Swartzlander Jr EE (2001) CDMA as a multiprocessor interconnect strategy. In: Conference record of 35th asilomar conference on signals, systems and computers, vol 2, pp 1246-1250. doi:10.1109/ACSSC.2001.987690

  14. Karmarkar K, Tragoudas S (2014) Error correction encoding for tightly coupled on-chip buses. IEEE Trans Very Large Scale Integr Syst 22(12):2571–2584. doi:10.1109/TVLSI.2014.2300095

    Article  Google Scholar 

  15. Lehtonen T, Wolpert D, Liljeberg P, Plosila J (2010) Self-adaptive system for addressing permanent errors in on-chip interconnects. IEEE Trans Very Large Scale Integr Syst 18(4):527–540. doi:10.1109/TVLSI.2009.2013711

    Article  Google Scholar 

  16. Sridhara SR, Shanbhag NR (2005) Coding for system-on-chip networks: a unified framework. IEEE Trans Very Large Scale Integr Syst 13(6):655–667. doi:10.1109/TVLSI.2005.848816

    Article  Google Scholar 

  17. Karmarkar K, Tragoudas S (2014) On-chip codeword generation to cope with crosstalk. IEEE Trans Comput-Aided Des Integr Circuits Syst 33(2):237–250. doi:10.1109/TCAD.2013.2284017

    Article  Google Scholar 

  18. Ganguly A, Pande PP, Belzer B (2009) Crosstalk-aware channel coding schemes for energy efficient and reliable NoC interconnects. IEEE Trans Very Large Scale Integr Syst 17(11):1626–1639. doi:10.1109/TVLSI.2008.2005722

    Article  Google Scholar 

  19. Chang KC (2011) Reliable network-on-chip design for multi-core system-on-chip. J Supercomput 55:86–102. doi:10.1007/s11227-009-0376-4

    Article  Google Scholar 

  20. Egwutuoha IP, Levy D, Selic B, Chen S (2013) A survey of fault tolerance mechanisms and checkpoint/restart implementations for high performance computing systems. J Supercomput 65:1302–1326. doi:10.1007/s11227-013-0884-0

    Article  Google Scholar 

  21. Namazi A, Nourani M, Saquib M (2010) A fault-tolerant interconnect mechanism for NMR nanoarchitectures. IEEE Trans Very Large Scale Integr Syst 18(10):1433–1446. doi:10.1109/TVLSI.2009.2024779

    Article  Google Scholar 

  22. Nikolic T, Nikolic G, Stojcev M, Stamenkovic Z (2015) Low-power fault-tolerant interconnect method based on LCDMA and duplication. Microelectron Reliab 55(1):272–281. doi:10.1016/j.microrel.2014.09.029

    Article  Google Scholar 

  23. Golubov B, Efimov A, Skvortsov V (1991) Walsh series and transforms: theory and applications. Kluwer, Springer, The Netherlands

    Book  MATH  Google Scholar 

  24. Chan AM, Feldman J, Madyastha R, Indyk P (2006) Low-complexity localized walsh decoding for CDMA systems. IEEE Mil Commun Conf MILCOM. doi:10.1109/MILCOM.2006.302017

    Google Scholar 

  25. Wicker S (1995) Error control systems for digital communication and storage. Prentice Hall, Englewood Cliffs

    MATH  Google Scholar 

Download references

Acknowledgments

This work was supported by the Serbian Ministry of Education, Science and Technological Development, Project No. TR-32009—“Low-Power Reconfigurable Fault-Tolerant Platforms”.

Author information

Authors and Affiliations

  1. Faculty of Electronic Engineering, University of Nis, A. Medvedeva 14, Nis, 18000, Serbia

    Tatjana R. Nikolic, Goran S. Nikolic, Goran Lj. Djordjevic & Mile K. Stojcev

Authors
  1. Tatjana R. Nikolic
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Goran S. Nikolic
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Goran Lj. Djordjevic
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Mile K. Stojcev
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Tatjana R. Nikolic.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Nikolic, T.R., Nikolic, G.S., Djordjevic, G.L. et al. Improving fault-tolerance capability of on-chip binary CDMA bus. J Supercomput 72, 275–294 (2016). https://doi.org/10.1007/s11227-015-1513-x

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-015-1513-x

Keywords

Search

Navigation