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Implications of shallower memory controller transaction queues in scalable memory systems

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Abstract

Scalable memory systems provide scalable bandwidth to the core growth demands in multicores and embedded systems processors. In these systems, as memory controllers (MCs) are scaled, memory traffic per MC is reduced, so transaction queues become shallower. As a consequence, there is an opportunity to explore transaction queue utilization and its impact on energy utilization. In this paper, we propose to evaluate the performance and energy-per-bit impact when reducing transaction queue sizes along with the MCs of these systems. Experimental results show that reducing 50 % on the number of entries, bandwidth and energy-per-bit levels are not affected, whilst reducing aggressively of about 90 %, bandwidth is similarly reduced while causing significantly higher energy-per-bit utilization.

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Acknowledgments

Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the Ministry of Science and Technology (MOST, Taiwan), Providence University and Nvidia. This research is based upon work partially supported by Ministry of Science and Technology (MOST, Taiwan), Providence University and NVIDIA. We would like to thank Maria Amelia Guitti Marino and anonymous reviewers for their feedbacks and suggestions.

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Authors and Affiliations

  1. Nuoro, Italy

    Mario D. Marino

  2. Department of Computer Science and Information Engineering (CSIE), Providence University, Taichung, Taiwan

    Kuan-Ching Li

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  1. Mario D. Marino
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  2. Kuan-Ching Li
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Correspondence to Kuan-Ching Li.

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Marino, M.D., Li, KC. Implications of shallower memory controller transaction queues in scalable memory systems. J Supercomput 72, 1785–1798 (2016). https://doi.org/10.1007/s11227-015-1485-x

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