Abstract
With the number of CPU cores on a processor chip increasing rapidly, conventional electronic interconnects for core-to-core communication have run into a bottleneck. Recently, rapid development has been achieved for photonic technologies, which makes optical network on chip become an emerging solution to breakthrough electronic interconnect limitations. Multistage optical network on chips (MONoCs), by adopting multiple stages in the architecture, have great potentials to achieve the advantages of energy efficiency, high performance and scalability. To benefit from these advantages, we design a novel system-level model for MONoCs, which allows us to evaluate the performance by modeling and analyzing the latency, loss and crosstalk. The model is validated by simulation, which demonstrates that we can identify and predict some potential problems, such as latency jitter and asymmetry insertion loss distribution. Results show that our proposed model can provide insightful guidance for designing multistage optical network on chip.
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Acknowledgements
This work is supported in part by the National Science Foundation of China under Grant Nos. 61634004, 61472300, 61474087 and 61334003, in part by the 111 Project under Grant No. B08038.
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Bai, L., Gu, H., Chen, Y. et al. System-level modeling and performance evaluation of multistage optical network on chips (MONoCs). Photon Netw Commun 34, 25–33 (2017). https://doi.org/10.1007/s11107-016-0670-z
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DOI: https://doi.org/10.1007/s11107-016-0670-z