Abstract
Testing for small-delay defects (SDDs) has become necessary as technology further scales. Existing tools and methodologies for generating SDD patterns suffer from: limited long-paths sensitization capability, overwhelming pattern volume, time-consuming pattern generation process, and vague evaluations of pattern quality. Such situation places patterns in a dilemma where the generation and application effort are huge yet the results cannot reflect the physical phenomena clearly enough for correct binning and diagnosis. In this paper, we focus on establishing a pattern generation flow that produces patterns of high application value. Firstly, critical faults are identified in order to generate high-quality original pattern repository with n-detect ATPG.A novelpattern evaluation and selection method that further minimizes pattern count while maintaining the SDD detection ability is then presented. Top-off ATPG is then performed to ensure meeting the target fault coverage. Along with the flow, multiple evaluation metrics are also proposed to measure the pattern’s efficiency on SDD coverage, unique SDD detection, detectable SDD size, long path distribution, etc. Experimental results demonstrate that the proposed critical fault-based method improves long path sensitization efficiency by 2.5× without impairing its average delay and saves approximately 80 % CPU runtime compared with total fault-based method. Comparing with timing-aware ATPG, the generated pattern set detects equivalent or even more SDDs with significantly reduced pattern count.
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References
Amyeen ME, Venkataraman S, Ojha A, Lee S (2004) Evaluation of the quality of N-Detect scan ATPG patterns on a processor. In: Proc. int test conf (ITC’04)
Cavenaghi P, Mattiuzzo R, Bahl S, Garg A (2010) Incremental small delay defect methodology. In: Proc. IEEE design automation conf (DAC’10)
Chen J, Bolin B, Wang L-C, Zeng J, Drmanac D, Mateja M (2010) Mining AC delay measurement for understanding speed-limiting paths. In: Proc. int test conf (ITC’10)
Goel S, Devta-Prasanna N, Turakhia R (2009) Effective and efficient test pattern generation for small delay defects. In: Proc. IEEE VLSI test symposium (VTS’09)
Goel S, Chakrabarty K, Yilmaz M, Peng K, Tehranipoor M (2010) Circuit topology-based test pattern generation for small-delay defects. In: Proc. IEEE Asian test symposium (ATS’10)
Gupta P, Hsiao MS (2004) ALAPTF: A new transition fault model and the ATPG algorithm. In: Proc. int test conf (ITC’04)
Huang Y (2006) On N-Detect pattern set optimization. In: Proc. IEEE international symposium on quality electronic design (ISQED’06)
IWLS (2005) Benchmarks. http://iwls.org/iwls2005/benchmarks.html
Lion J, Krstic A, Wang L, Cheng K-T (2002) False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. In: Proc. IEEE design automation conference (DAC’02)
Ma JX, Tehranipoor M (2011) Layout-aware critical path delay test under maximum power supply noise effects. IEEE Trans Computer-aided Des Integr Circuits Syst 30(12):1923–1934
Ma JX, Ahmed N, Tehranipoor M (2011) Low-cost diagnostic pattern generation and evaluation procedures for noise-related failures. In: Proc. IEEE European test symposium (ETS’11)
Mattiuzzo R, Appello D (2009) Small delay defect testing. http://www.tmworld.com/article/CA6660051.html. Test & measurement world
Mentor Graphics (2008) Timing-aware ATPG_fastscan mentor datasheet
Peng K, Yilmaz M, Tehranipoor M, Chakrabarty K (2010) Highquality pattern selection for screening small-delay defects considering process variations and crosstalk. In: IEEE design automation & test in Europe (DATE’10)
Peng K, Thibodeau J, Yilmaz M, Chakrabarty K, Tehranipoor M (2010) A novel hybrid method for sdd pattern grading and selection. In: Proc. IEEE VLSI test symposium (VTS’10)
Qiu W, Wang J, Walker D, Reddy D, Xiang L, Zhou L, Shi W, Balachandran H (2004) K longest paths per gate (KLPG) test generation for scan scan-based sequential circuits. In: Proc. int test conf (ITC’04)
Synopsys Inc. (2010) TetraMAX ATPG user guide, Synopsys datasheet
Tayade R, Abraham JA (2009) Critical path selection for delay test considering coupling noise. In: Proc. IEEE European test symposium (ETS’09)
Wang L-C, Liou J-J, Cheng K-T (2004) Critical Path selection for delay fault testing based upon a statistical timing model. IEEE Trans Comput-aided Des Integr Circuits Syst 23(11):1550–1565
Yilmaz M, Chakrabarty K, Tehranipoor M (2008) Test-pattern grading and pattern selection for small-delay defects. In: Proc. IEEE VLSI test symposium (VTS’08)
Yilmaz M, Chakrabarty K, Tehranipoor M (2010) Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits. IEEE Trans Compu-aided Des Integr Circuits Syst 29(5):760–773
Zeng J, Abadir M, Vandling G, Wang L, Kolhatkar A, Abraham J (2004) On correlating structual tests with functional tests for speed binning of high performance design. In: Proc. int test conf (ITC’04)
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Responsible Editor: C. Metra
The work of F. Bao, K. Peng and M. Tehranipoor was supported in part by NSF under Grants no. ECCS-0823992 and CCF-0811632.
The work of K. Chakrabarty was supported in part by SRC under Contract No. 1588 and by NSF under Grant no. ECCS-0823835.
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Bao, F., Peng, K., Yilmaz, M. et al. Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults. J Electron Test 29, 35–48 (2013). https://doi.org/10.1007/s10836-012-5345-9
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DOI: https://doi.org/10.1007/s10836-012-5345-9