Abort-on-Fail Based Test Scheduling
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The long and increasing test application time for modular core-based system-on-chips is a major problem, and many approaches have been developed to deal with the problem. Different from previous approaches, where it is assumed that all tests will be performed until completion, we consider the cases where the test process is terminated as soon as a defect is detected. Such abort-on-fail testing is common practice in production test of chips. We define a model to compute the expected test time for a given test schedule in an abort-on-fail environment. We have implemented three scheduling techniques and the experimental results show a significant test time reduction (up to 90%) when making use of an efficient test scheduling technique that takes defect probabilities into account.
- M.L. Flottes, J. Pouget, and B.Rouzeyre, “Sessionless Test Scheme: Power-constrained Test Scheduling for System-on-a-Chip,” Proceedings of the 11th IFIP on VLSI-SoC, Montpellier, 2001, pp. 105–110.
- P. Harrod, “Testing reusable IP-a case study,” in Proceedings of International Test Conference (ITC), Atlantic City, NJ, USA, 1999, pp. 493–498.
- Y. Huang, W.-T. Cheng, C.-C. Tsai, N. Mukherjee, O. Samman, Y. Zaidan, and S.M. Reddy, “Resource Allocation and Test Scheduling for Concurrent Test of Core-based SOC Design,” in Proceedings of IEEE Asian Test Symposium (ATS), Kyoto, Japan, 2001, pp. 265–270.
- S.D. Huss and R.S. Gyurcsik, “Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time,” in Proceedings of the ACM/IEEE Design Automation Conference (DAC), 1991, pp. 494–499.
- V. Iyengar, and K. Chakrabarty, and E.J. Marinissen, “Test Wrapper and Test Access Mechanism Co-Optimization for System-On-Chip,” in Proceedings of International Test Conference (ITC), Baltimore, MD, USA, 2001, pp. 1023–1032.
- V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip,” Transactions on Computers, vol. 52, no. 12, pp. 1619–1632, 2003.
- W.J. Jiang and B. Vinnakota, “Defect-Oriented Test Scheduling,” IEEE Transactions on Very-Large Scale Integration (VLSI) Systems, vol. 9, no. 3, pp. 427–438, 2001.
- S. Koranne, “On Test Scheduling for Core-Based SOCs,” in Proceedings of the IEEE International Conference on VLSI Design (VLSID), Bangalore, India, January 2002, pp. 505–510.
- E.J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters, “A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores,” in Proceedings of International Test Conference (ITC), Washington, DC, USA, 1998, pp. 284–293.
- E.J. Marinissen, V. Iyengar, and K. Chakrabarty, “A Set of Benchmarks for Modular Testing of SOCs,” in Proceedings of International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 519–528.
- L. Milor and A.L. Sangiovanni-Vincentelli, “Minimizing Production Test Time to Detect Faults in Analog Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 6, pp. 796–, 1994.
- J. Pouget, E. Larsson, and Z. Peng, “SOC Test Time Minimization Under Multiple Constraints,” in Proceedings of Asian Test Symposium (ATS), Xian, China, 2003.
- J. Pouget, E. Larsson, Z. Peng, M.L. Flottes, and B. Rouzeyre, “An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling,” Formal Proceedings of European Test Workshop 2003 (ETW '03), Maastricht, The Netherlands, 2003, pp. 51–56.
- P. Varma and S. Bhatia, “A Structured Test Re-Use Methodology for Core-based System Chips,” in Proceedings of International Test Conference (ITC), Washington, DC, USA, 1998, pp. 294–302.
- Abort-on-Fail Based Test Scheduling
Journal of Electronic Testing
Volume 21, Issue 6 , pp 651-658
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- SoC testing
- test scheduling
- defect probability
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