Multiple-Constraint Driven System-on-Chip Test Time Optimization
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The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC'02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.
- R.M. Chou, K.K. Saluja, and V.D. Agrawal, “Scheduling Tests for VLSI Systems Under Power Constraints,” IEEE Transactions on VLSI Systems, vol. 5, no. 2, pp. 175–185, 1997.
- E. Cota, L. Cairo, M. Lubaszewski, and A. Orailoglu, “Test Planning and Design Space Exploration in a Core-based Environment,” in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Paris, France, 2002, pp. 478–485.
- H-S Hsu, J-R Huang, K-L Cheng, C-W Wang, C-T Huang, and C-W Wu, “Test Scheduling and Test Access Architecture Optimization for System-on-Chip,” in Proceedings of IEEE Asian Test Symposium (ATS), Tamuning, Guam, USA, 2002, pp. 411–416.
- Y. Huang, S.M. Reddy, W-T Cheng, P. Reuter, N. Mukherjee, C-C Tsai, O. Samman, and Y. Zaidan, “Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm,” in Proceedings IEEE of International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 74–82.
- V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip,” Journal of Electronic Testing; Theory and Applications (JETTA), pp. 213–230, 2002.
- V. Iyengar K. Chakrabarty, and E.J. Marinissen, “Efficient Wrapper/TAM Co-Optimization for Large SOCs,” in Proceedings of Design and Test in Europe (DATE), Paris, France, 2002, pp. 491–498.
- V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization,” in Proceedings of IEEE VLSI Test Symposium (VTS), Monterey, California, USA, 2002, pp. 253–258.
- V. Iyengar, S.K. Goel, E.J. Marinissen, and K. Chakrabarty, “Test Resource Optimization for Multi-Site Testing of SOCs under ATE Memory Depth Constraints,” in Proceedings of IEEE International Test Conference, Baltimore, MD, USA, 2002, pp. 1159–1168.
- V. Iyengar, K. Chakrabarty, M.D. Krasniewski, and G.N. Kuma, “Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs,” in Proceedings of IEEE VLSI Test Symposium (VTS), 2003, pp. 299–304.
- S.K. Goel and E.J. Marinissen, “Cluster-Based Test Architecture Design for System-On-Chip,” in Proceedings of IEEE VLSI Test Symposium (VTS), Monterey, California, USA, 2002, pp. 259–264.
- S.K. Goel and E.J. Marinissen, “Effective and efficient test architecture design for SOCs,” in Proceedings of IEEE International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 529–538.
- S. Koranne, “On Test Scheduling for Core-based. SOCs,” in Proceedings of International Conference on VLSI Design, Bangalore, India, 2002, pp 505–510.
- S. Koranne and V. Iyengar, “On the use of k - tuples for SoC test schedule representation,” in Proceedings of International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 539–548.
- E.J. Marinissen, R. Kapur, and Y. Zorian, “On Using IEEE P1500 SECT for Test Plug-n-play,” in Proceedings of IEEE International Test Conference (ITC), Atlantic City, NJ, USA, 2000, pp. 770–777.
- J. Pouget, E. Larsson, Z. Peng, M.-L. Flottes, and B. Rouzeyre, “An Efficient Approach to SoC Wrapper Design, TAM configuration, and Test Scheduling,” in Proceedings of IEEE European Test Workshop (ETW), Maastricht, The Nederlands, 2003, pp. 117-122.
- J. Pouget, E. Larsson, and Z. Peng, “SOC Test Time Minimization Under Multiple Constraints,” in Proceedings of Asian Test Symposium (ATS), Xian, China, 2003, pp. 312–317.
- Multiple-Constraint Driven System-on-Chip Test Time Optimization
Journal of Electronic Testing
Volume 21, Issue 6 , pp 599-611
- Cover Date
- Print ISSN
- Online ISSN
- Kluwer Academic Publishers
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- SOC testing
- multiple constraints
- wrapper and TAM design
- test scheduling
- power constraint
- Industry Sectors