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Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

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Abstract

The gate-all-around (GAA) CNTFET is one of the most efficient types of CNTFETs which provides the conditions for scaling the technology to 10 nm and beyond, due to the extraordinary features of carbon nanotubes and the superior gate control through a high-k insulator over the CNT channel. However, the high CNT-metal contact resistance at the source/drain terminals can significantly degrade the device and circuit performance in CNTFET technology compared to what we have expected. In this study, first a comprehensive comparative assessment of performance and robustness of the gate-all-around CNTFET- and FinFET-based devices and circuits is performed. In the GAA CNTFET-based circuits the contact resistance can be defined as a series resistor at each contacted node of transistors. In addition, an effective circuit-level solution for improving the performance of GAA CNTFET-based circuits in the presence of contact resistance is proposed. In this approach, the contact lengths of the devices located on the critical path are increased to an effective value to reduce the contact resistance considerably and the other contact lengths remain minimum-sized. The results demonstrate that applying this solution significantly improves the speed, energy consumption and energy-delay product of GAA CNTFET-based circuits.

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References

  1. Franklin, D., Luisier, M., Han, S.-J., Tulevski, G., Breslin, C.M., Gignac, L., Lundstrom, M.S., Haensch, W.: Sub-10 nm carbon nanotube transistor. Nano Lett. 12(2), 758–762 (2012)

    Article  Google Scholar 

  2. Sharifi, F., Moaiyeri, M.H., Navi, K., Bagherzadeh, N.: Quaternary full adder cells based on carbon nanotube FETs. J. Comput. Electron. 14(3), 762–772 (2015)

    Article  Google Scholar 

  3. Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.-J., Bokor, J., Hu, C.: FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47(12), 2320–2325 (2000)

    Article  Google Scholar 

  4. Choi, Y.-K., Lindert, N., Xuan, P., Tang, S., Ha, D., Anderson, E., King, T.-J., Bokor, J., Hu, C.: Sub-20 nm CMOS FinFET technologies. In: International Electron Devices Meeting, IEDM’01, pp. 19.1.1–10.1.4 (2001)

  5. Hu, T.J., King, V., Subramanian, L., Chang, X., Huang, Y.K., Choi, J.T., Kedzierski, N., Lindert, J., Bokor, W., Lee, W.C.: FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture. U.S. Patent No. 6,413,802. 2 July (2002)

  6. Aller, I., Gernhoefer, V., Keinert, J., Ludwig, T.: Method and device for automated layer generation for double-gate FinFET designs. U.S. Patent No. 7,315,994. 1 Jan (2008)

  7. Liang, J., Chen, L., Han, J., Lombardi, F.: Design and evaluation of multiple valued logic gates using pseudo N-Type carbon nanotube FETs. IEEE Trans. Nanotechnol. 13(4), 695–708 (2014)

    Article  Google Scholar 

  8. Tyagi, A., Gopi, C., Baldi, P., Islam, A.: CNFET-based 0.1- to 1.2-V DC/DC boost converter with voltage regulation for energy harvesting applications. IEEE Trans. Nanotechnol. 14(4), 660–667 (2015)

    Article  Google Scholar 

  9. Rezaeikhezeli, M., Moaiyeri, M.H., Jalali, Ali: Analysis of crosstalk effects for multiwalled carbon nanotube bundle interconnects in ternary logic and comparison with Cu interconnects. IEEE Trans. Nanotechnol. 16(1), 107–117 (2017)

    Google Scholar 

  10. Deng, J., Wong, H.S.P.: A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part I: model of the intrinsic channel region. IEEE Trans. Electron Devices 54(12), 3186–3194 (2007)

    Article  Google Scholar 

  11. Deng, J., Wong, H.S.P.: A Compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Devices 54(12), 3195–3205 (2007)

    Article  Google Scholar 

  12. Marani, R., Gelao, G., Perri, A.G.: Comparison of ABM SPICE library with verilog-A for compact CNTFET model implementation. Curr. Nanosci. 8(4), 556–565 (2014)

    Article  Google Scholar 

  13. Frégonèse, S., d’Honincthun, H.C., Goguet, J., Maneux, C., Zimmer, T., Bourgoin, J.-P., Dollfus, P., Galdin-Retailleau, S.: Computationally efficient physics-based compact CNTFET model for circuit design. IEEE Trans. Electron Devices 55(6), 1317–1327 (2008)

    Article  Google Scholar 

  14. Schröter, M., Haferlach, M., Pacheco-Sanchez, A., Mothes, S., Sakalas, P., Claus, M.: A semiphysical large-signal compact carbon nanotube FET model for analog RF applications. IEEE Trans. Electron Devices 62(1), 52–60 (2015)

    Article  Google Scholar 

  15. Marani, R., Perri, A.G.: A simulation study of analogue and logic circuits with CNTFETs. ECS J. Solid State Sci. Technol. 5(6), M38–M43 (2016)

    Article  Google Scholar 

  16. Moaiyeri, M.H., Doostaregan, A., Navi, K.: Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits Devices Syst. 5(4), 285–296 (2011)

    Article  MATH  Google Scholar 

  17. Lee, C.-S., Pop, E., Franklin, A.D., Haensch, W., Wong, H.-S.: A compact virtual-source model for carbon nanotube FETs in the Sub-10-nm regime—Part I: intrinsic elements. IEEE Trans. Electron Devices 62(9), 3061–3069 (2015)

    Article  Google Scholar 

  18. Lee, C.-S., Pop, E., Franklin, A.D., Haensch, W., Wong, H.-S.P.: A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—Part II: extrinsic elements, performance assessment, and design optimization. IEEE Trans. Electron Devices 62(9), 3070–3078 (2015)

  19. Luo, J., Wei, L., Lee, C.S., Franklin, A.D., Guan, X., Pop, E., Antoniadis, D.A., Wong, H.S.P.: Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length. IEEE Trans. Electron Devices 60(6), 1834–1843 (2013)

    Article  Google Scholar 

  20. https://nano.stanford.edu/stanford-cnfet2-model

  21. Raychowdhury, A., Roy, K.: Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54(11), 2391–2401 (2007)

    Article  Google Scholar 

  22. Khakifirooz, A., Nayfeh, O.M., Antoniadis, D.: A simple semiempirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters. IEEE Trans. Electron Devices 56(8), 1674–1680 (2009)

    Article  Google Scholar 

  23. Paydavosi, N., Venugopalan, S., Chauhan, Y.S., Duarte, J.P., Jandhyala, S., Niknejad, A.M., Hu, C.C.: BSIM–SPICE models enable FinFET and UTB IC designs. IEEE Access 1, 201–215 (2013)

    Article  Google Scholar 

  24. Dunga, M.V., Lin, C.-H., Niknejad, A.M., Hu, C.: BSIM-CMG: a compact model for multi-gate transistors. In: FinFETs and Other Multi-Gate Transistors, pp. 113–153. Springer, New York (2008)

  25. http://ptm.asu.edu/

  26. Sinha, S., Yeric, G., Chandra, V., Cline, B., Cao, Y.: Exploring Sub-20 nm FinFET design with predictive technology models. In: Proceedings of the 49th Annual Design Automation Conference (DAC), pp. 283-288 (2012)

  27. Javey, A., Guo, J., Wang, Q., Lundstrom, M., Dai, H.J.: Ballistic carbon nanotube field-effect transistors. Nature 424(6949), 654–657 (2003)

    Article  Google Scholar 

  28. Liu, W., Hierold, C., Haluska, M.: Electrical contacts to individual SWCNTs: a review. Beilstein J. Nanotechnol. 5(1), 2202–2215 (2014)

    Article  Google Scholar 

  29. Chai, Y., Hazeghi, A., Takei, K., Chen, H.Y., Chan, P.C.H., Javey, A., Wong, H.S.P.: Low-resistance electrical contact to carbon nanotubes with graphitic interfacial layer. IEEE Trans. Electron Devices 59(1), 12–19 (2012)

    Article  Google Scholar 

  30. Choi, Y.-K., Chang, L., Ranade, P., Lee, J.-S., Ha, D., Balasubramanian, S., Agarwal, A., Ameen, M., King, T.-J., Bokor, J.: FinFET process refinements for improved mobility and gate work function engineering. In: International 2002 Electron Devices Meeting, IEDM’02 pp. 259–262 (2002)

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Acknowledgements

The authors would like to thank Dr. Chi-Shuen Lee at Stanford University for the many useful discussions and fruitful collaborations.

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Authors and Affiliations

  1. Faculty of Electrical Engineering, Shahid Beheshti University, G.C, Tehran, Iran

    Mohammad Hossein Moaiyeri

  2. Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, G.C, Tehran, Iran

    Farzad Razi

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  1. Mohammad Hossein Moaiyeri
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  2. Farzad Razi
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Correspondence to Mohammad Hossein Moaiyeri.

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Moaiyeri, M.H., Razi, F. Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance. J Comput Electron 16, 240–252 (2017). https://doi.org/10.1007/s10825-017-0980-0

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  • DOI: https://doi.org/10.1007/s10825-017-0980-0

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