Skip to main content
SpringerLink
Log in

Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits

  • Published:
Journal of Computational Electronics Aims and scope Submit manuscript

Abstract

Reversible logic has attracted interest from many researchers in the area of quantum information science. Since there is no information loss in reversible logic, energy consumption is greatly reduced. However, realization of quantum equivalent circuits using cascading reversible gates is complex. Predominantly, this work targets implementation of quantum equivalent circuits using cascading reversible gates. In this work, novel code converters and a dual-rail checker with lower cost metrics such as gate count, garbage output, ancilla input, unit delay, logical calculation, and quantum cost are constructed. Several new reversible gates, namely BE (binary excess), BG-2 (binary Gray), GB-2 (Gray binary), and NG-R1 and NG-R2 (N \(=\) new, R \(=\) reversible), are designed and used to construct efficient code converter and dual-rail checker circuits. The main contribution of these novel circuits is the consideration of the gate-level schematics in the respective quantum equivalent circuit using our proposed algorithm. The performance results establish that the novel binary-coded decimal (BCD)-to-excess-3, binary-to-Gray, and dual-rail checker achieve improvement of 25 and 66.6 % in gate count and 44.4 % in quantum cost, respectively, compared with counterpart designs.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. Dueck, G.W.: Challenges and advances in Toffoli network optimization. IET Comput. Digit. Tech. 8(4), 172–177 (2014)

    Article  MathSciNet  Google Scholar 

  2. De Vos, A.: Alexis: ‘Reversible Computing: Fundamentals, Quantum Computing, and Applications’, p. 261. Wiley (2011)

  3. Maslov, D., Saeedi, M.: Reversible circuit optimization via leaving the Boolean domain. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6), 806–816 (2011)

    Article  Google Scholar 

  4. Gaur, H.M., Singh, A.K.: Design of reversible circuits with high testability. Electron. Lett. 52(13), 1102–1104 (2016)

    Article  Google Scholar 

  5. Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183–191 (1961)

    Article  MathSciNet  MATH  Google Scholar 

  6. Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973)

    Article  MathSciNet  MATH  Google Scholar 

  7. Athas, W.C., Svensson, L.J.: Reversible logic issues in adiabatic CMOS. IEEE Proceedings Workshop on Physics and Computation PhysComp’94, pp. 111–118 (1994)

  8. Thomsen, M.K., Glück, R.: Reversible arithmetic logic unit for quantum arithmetic. J. Phys. A: Math. Theor. 43(38), 382002 (2010)

    Article  MathSciNet  MATH  Google Scholar 

  9. Houri, S., Valentian, A., Fanet, H.: Comparing CMOS-based and NEMS-based adiabatic logic circuits. In: 5th International Conference on Reversible Computation, Victoria, BC, Canada, pp. 36–45. Springer, Berlin, Heidelberg (2013)

  10. Shamsujjoha, M., Hossain, F., Ali, M.N.Y., Babu, H.M.H.: Optimized fault tolerant designs of the reversible barrel shifters using low power MOS transistors. J. Comput. Electron. 14(3), 726–746 (2015)

    Article  Google Scholar 

  11. Knil, E., Laflamme, R., Milburn, G.J.: A scheme for efficient quantum computation with linear optics. Nature 409, 46–52 (2001)

    Article  Google Scholar 

  12. Chabi, A.M., Roohi, A., Khademolhosseini, H., Sheikhfaal, S., Angizi, S., Navi, K., DeMara, R.F.: Towards ultra-efficient QCA reversible circuits. Microsyst. Microprocess. (2016). doi:10.1016/j.micpro.2016.09.015

  13. Abdessaied, N., Amy, M., Drechsler, R., Soeken, M.: Complexity of reversible circuits and their quantum implementations. Theor. Comput. Sci. 618, 85–106 (2016)

    Article  MathSciNet  MATH  Google Scholar 

  14. Yang, G., Song, X., Perkowski, M.A., Hung, W.N.N., Biamonte, J., Tang, Z.: Four-level realisation of 3-qubit reversible functions. IET Comput. Digit. Tech. 1(4), 382–388 (2007)

    Article  Google Scholar 

  15. Sen, B., Ganeriwal, S., Sikdar, B.K. Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA, pp. 1–9. ISRN Electronics (2013)

  16. Li, M.-C., Zhou, R.-G.: A novel reversible carry-selected adder with low latency. Int. J. Electron. 103(7), 1202–1215 (2016)

    Article  MathSciNet  Google Scholar 

  17. Akbar, E.P.A., Haghparast, M., Navi, K.: Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology. Microelectron. J. 42(8), 973–981 (2011)

    Article  Google Scholar 

  18. Sen, B., Dutta, M., Some, S., Sikdar, B.K.: Realizing reversible computing in QCA framework resulting in the efficient design of testable ALU. ACM J. Emerg. Technol. Comput. Syst: JETC 11(3), 30 (2014)

    Article  Google Scholar 

  19. Thapliyal, H., Ranganathan, N.: Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM J. Emerg. Technol. Comput. Syst: JETC 6(4), 14 (2010)

    Article  Google Scholar 

  20. Haghparast, M., Hajizadeh, M., Hajizadeh, R., Bashiri, R.: On the synthesis of different nanometric reversible converters. Middle-East J. Sci. Res. 7(5), 715–720 (2011)

    Google Scholar 

  21. Saravanan, M., Suresh Manic, K.: Energy efficient code converters using reversible logic gates. In: IEEE International Conference on Green High Performance Computing (ICGHPC), pp. 1–6 (2013)

  22. Gandhi, S.M., Devishree, J., Venkatesh, J., Mohan, S.S.: Design of reversible circuit for code converter and binary incrementer. Int. J. Inf. Technol. Mech. Eng. 1(4), 24–33 (2014)

    Google Scholar 

  23. Kamani, K., Koneti, S., Boolampalli, U., Shankara, S.: Energy efficient reversible logic design of code converter. In: IEEE International Conference on Green High Performance Computing (ICGHPC), vol. 1, no 3, pp. 132–136 (2014)

  24. Das, J.C., De, D.: Reversible binary to grey and grey to binary code converter using QCA. IETE J. Res. 61(3), 223–229 (2015)

    Article  Google Scholar 

  25. Sasamal, T.N., Singh, A.K., Mohan, A.: Design of two-rail checker using a new parity preserving reversible logic gate. Int. J. Comput. Theory Eng. 7(4), 3–11 (2015)

    Article  Google Scholar 

  26. Vasudevan, D., Lala, P.K., Di, J., Parkerson, J.P.: Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. 55(2), 406–414 (2006)

    Article  Google Scholar 

  27. Misra, N.K., Wairya, S., Singh, V.K.: Optimized approach for reversible code converters using quantum dot cellular automata. In: Proceedings of the 4th International Conference on Frontiers in Intelligent Computing: Theory and Applications (FICTA), Springer India, pp. 367–378 (2015)

  28. Große, D., Wille, R., Dueck, G.W., Drechsler, R.: Exact synthesis of elementary quantum gate circuits. Mult Valued Log. Soft Comput. 15(4), 283–300 (2009)

    MathSciNet  MATH  Google Scholar 

  29. Wille, R., Lye, A., Drechsler, R.: Considering nearest neighbor constraints of quantum circuits at the reversible circuit level. Quantum Inf. Process. 13(2), 185–199 (2014)

    Article  MATH  Google Scholar 

  30. Sasanian, Z., Wille, R., Miller, D.M.: Clarification on the Mapping of Reversible Circuits to the NCV-v1 Library. arXiv preprint, arXiv:1309.1419 (2013)

Download references

Acknowledgements

The authors would like to thank the anonymous reviewers for their constructive criticism and effective advice that improved a preliminary version of this paper.

Author information

Authors and Affiliations

  1. Department of Electronics Engineering, Institute of Engineering and Technology, Lucknow, India

    Neeraj Kumar Misra & Subodh Wairya

  2. Department of Computer Science and Engineering, National Institute of Technology, Durgapur, India

    Bibhash Sen

Authors
  1. Neeraj Kumar Misra
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Bibhash Sen
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Subodh Wairya
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Neeraj Kumar Misra.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Misra, N.K., Sen, B. & Wairya, S. Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits. J Comput Electron 16, 442–458 (2017). https://doi.org/10.1007/s10825-017-0960-4

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10825-017-0960-4

Keywords

Search

Navigation