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A modified macro model approach for SPICE based simulation of single electron transistor

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Abstract

A new macro model of single electron transistor (SET) for SPICE based simulation of SET circuits is proposed. Two voltage controlled current sources and some scaling factors are incorporated in the existing model to derive our model. The V–I characteristics of the proposed SET is promising enough to be used as the basic element for designing circuits based on SETs. A comparison with the previous models establishes the fact that our model efficiently removes the drawbacks of the existing models. Our model also agrees well with the results obtained from popular SIMON simulator. To verify the accuracy, we have designed a SET inverter cell and investigated its characteristics. The work includes the effect of the parameters on the noise margin and voltage transfer characteristics of the inverter circuit. Further, to verify the applicability, a multi peak negative differential resistance circuit based on the proposed model is designed and simulated.

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Acknowledgments

Subir Kumar Sarkar thankfully acknowledges the financial support obtained from UGC UPE-Phase II project, Jadavpur University.

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Authors and Affiliations

  1. Department of ECE, RCCIIT, Kolkata, 700015, India

    Arpita Ghosh

  2. Department of ETCE, Jadavpur University, Kolkata, 700032, India

    Amit Jain & Subir Kumar Sarkar

  3. Department of ECE, Manipur Institute of Technology, Manipur University, Imphal, 795004, India

    N. Basanta Singh

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  1. Arpita Ghosh
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  2. Amit Jain
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  3. N. Basanta Singh
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  4. Subir Kumar Sarkar
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Correspondence to Arpita Ghosh.

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Ghosh, A., Jain, A., Singh, N.B. et al. A modified macro model approach for SPICE based simulation of single electron transistor. J Comput Electron 15, 400–406 (2016). https://doi.org/10.1007/s10825-015-0790-1

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  • DOI: https://doi.org/10.1007/s10825-015-0790-1

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