A compact modelling of double-walled gate wrap around carbon nanotube array field effect transistors

Abstract

The effects of multi-walled CNTs and array of channels are combined to form Double-walled Gate Wrap Around Carbon Nano Tube array Field Effect Transistor (DWGWA CNTFET). Numerical model is proposed for the device to study its performance. Screening and imaging effects of adjacent and inter walls in array of channels are included for calculating the drive capacitance, subsequently the drive current. This model suits for a wide range of chiralities and diameters. The change in drive capacitance of double-walled and single-walled device with respect to various drain and gate voltage for different values of number of channels, diameters are studied. The number of channels, CNTs diameters, chiralities of the tubes, source/drain length are varied and the corresponding responses of drive current, cut off frequency, signal delay time for both double and single walled devices are compared. In all cases, DWGWA CNTFET excels in its performance over Single-walled Gate Wrap Around Carbon Nano Tube array Field Effect Transistor (SWGWA CNTFET).The model of the proposed device can be utilized for designing the Nano devices with high power and high speed capability.

Appendices

Appendix 1

The equations for the following three capacitances considered in [14] for gate wrap around is taken for discussion in our paper.

• (a) Gate to channel Capacitance (Cgc)

• (b) Fringe Capacitance and (Cof)

• (c) Gate to gate capacitance (or) gate to source/drain capacitance (Cgtg)

(a) Gate to channel capacitance (Cgc)

There are two calculations for Gate to channel capacitance (Cgc), since both individual walls of the channel are to be taken separately. One is the capacitance due to gate and outer wall of the channel (Cgc,o) and the other is due to capacitance between gate and inner wall of the channel $(Cgc,I)$.

Cgc,o is further divided into

• (a) Gate channel capacitance of the outer wall and the screening effects of other DWCNTs $({Cgc,o}^{(o)(o)})$ and

• (b) Gate channel capacitance due to imaging effects of the inter walls of the same channel $({Cgc,o}^{(o)(I)})$.

They are related by the following equations as in [10] and [11].

$$\begin{aligned} Cgc,o=\frac{1}{\frac{1}{Cgc,o^{(o)(o)}}+\frac{1}{Cgc,o^{(o)(I)}}} \end{aligned}$$

(28)

The reason behind to take Eq. (1) from [11] is that double wall is considered in this paper and the equations are similar for planar [11] and gate wrap around [14].

Again, $Cgc^{(o)(o)}$ can be divided for capacitance of the channels at

• (i) end of the array $({Cgc,e}^{(o)(o)})$ caused by the neighbouring channel at one side alone and

• (ii) middle of the array $({Cgc,m}^{(o)(o)})$ caused by the neighbouring channel at both the sides.

They are calculated using the relations from [10, 11] and [14]

$$\begin{aligned} Cgc,o^{(o)(o)}=\left\{ {{\begin{array}{l} {Cgc,e^{(o)(o)}=\frac{Cgc,inf.Cgc,sr}{Cgc,inf+Cgc,sr}} \\ {Cgc,m^{(o)(o)}=2.Cgc,e^{(o)(o)}-Cgc,inf} \\ \end{array} }} \right. \nonumber \\ \end{aligned}$$

(29)

where Cgc,inf is the gate channel (outer wall) capacitance without any screening effects, Cgc,sr the equivalent capacitance including the screening effects of the other channels in the array.

Cgc,inf is calculated for cylindrical Gate Wrap Around CNTFET, the ratio $\frac{1}{3}$ in second term of denominator of Eq. (3) is for cylindrical gate wrap around as in [14].

$$\begin{aligned} Cgc,inf=\frac{2\pi \kappa _1 \varepsilon _0 }{\cosh ^{-1}\left( {\frac{2h}{d_o }} \right) +\frac{1}{3}\lambda _1 \ln \left( {\frac{2h+2d_o }{3d_o }} \right) } \end{aligned}$$

(30)

Cgc,sr is calculated by taking the potential drop

• (i) between gate and outer wall of the same channel and

• (ii) due to the screening effects of the double walls of the neighbouring DWCNTs [10] and [11].

$$\begin{aligned} Cgc,sr=\frac{1}{\frac{1}{Cgc,sr^{(o)(o)}}+\frac{1}{Cgc,sr^{(o)(I)}}} \end{aligned}$$

(31)

where,

$$\begin{aligned} Cgc,sr^{(o)(o)}=\frac{4\pi \kappa _1 \varepsilon _0 }{\ln \left( {\frac{s^{2}+2\left( {h-r_o } \right) .\left[ {h+\sqrt{h^{2}-r_o ^{2}}} \right] }{s^{2}+2\left( {h-r_o } \right) .\left[ {h-\sqrt{h^{2}-r_o ^{2}}} \right] }} \right) +\ln \left( {\frac{s^{2}+2\left( {h-r_o } \right) .\left[ {h+\sqrt{h^{2}-r_o ^{2}}} \right] }{s^{2}+2\left( {h-r_o } \right) .\left[ {h-\sqrt{h^{2}-r_o ^{2}}} \right] }} \right) +\lambda _1 \ln \left( {\frac{\left( {h+d_o } \right) ^{2}+s^{2}}{9r_o^2 +s^{2}}} \right) .tanh\left( {\frac{h+r_o }{s-d_o }} \right) } \end{aligned}$$

(32)

Equation (5) is taken from [14] (gate wrap around transistor). The term highlighted in blue is for gate wrap around transistors.

Here,

$$\begin{aligned} Cgc,sr^{(o)(I)}&= \frac{Q_A^{(o)} }{Q_A^{(I)} }Cgc,sr^{(o)(o)}\end{aligned}$$

(33)

$$\begin{aligned} Cgc,o^{(o)(I)}&= \frac{Q_A^{(o)} }{Q_A^{(I)} }Cgc,inf \end{aligned}$$

(34)

Equation (6) and (7) are derived with (5) [14] with the format of device containing the channel as double wall [11].

To find out Gate and inner wall of the channel (Cgc,I) [10], comprising

• (i) The effects of inhomogeneous gate dielectric and the imaging effects of other neighbouring GWADWCNTs $Cgc,I^{\left( I \right) (o)}$.

• (ii) The imaging effects of the outer wall $Cgc,I^{\left( I \right) (I)}$,

$$\begin{aligned}&Cgc,I=\frac{1}{\frac{1}{Cgc,o^{\left( I \right) (o)}}+\frac{1}{Cgc,o^{\left( I \right) (I)}}}\end{aligned}$$

(35)

$$\begin{aligned}&Cgc,I^{(I)(o)}=\frac{Q_A^{\left( I \right) (o)} }{Q_A^{(o)} }Cgc,o\end{aligned}$$

(36)

$$\begin{aligned}&\hbox {Cgc, I}^{(\mathrm{I})(\mathrm{I})}=\frac{2\pi \varepsilon _0}{\hbox {ln}\left( {\frac{\hbox {d}_\mathrm{o} }{\hbox {d}_\mathrm{I} }} \right) } \end{aligned}$$

(37)

where do and are $\hbox {d}_{\mathrm{I}}$ diameters of the cylinder, $a$ is Lattice Constant $(2.49\,\AA )$.

Equations (8), (9) and (10) are for double wall channelled array device, so it is taken from [11] and the corresponding values of gate wrap around from (1) is substituted for $Cgc,o$.

Next is about the fringing capacitance,

For wrap around gate FET equation (11) and (12) are taken from [14], the difference with respect to planar gate is highlighted in blue.

$$\begin{aligned} Cof,m&= \frac{2\alpha }{\eta _1 }Cof,e\nonumber \\&+\left( {\frac{1-2\alpha }{\eta _1 }} \right) .\left( {\frac{\pi \kappa _2 \varepsilon _0 Lsd}{1/3\,\cosh ^{-1}\left( {\frac{\left( {4h^{2}} \right) +(0.56Lsd)^{2}}{d_o }} \right) }} \right) \nonumber \\ \end{aligned}$$

(38)

where,

$$\begin{aligned}&\alpha =\exp \left( {\frac{N-3}{\tau _2 N}} \right) ,N\ge 3\end{aligned}$$

(39)

$$\begin{aligned}&Cof,e =\frac{\pi \kappa _2 \varepsilon _0 Lsd}{\ln \left( {\frac{\left( {4h^{2}} \right) +(0.56Lsd)^{2}+s^{2}}{s}} \right) +\ln \left( {\frac{\sqrt{\left( {s/2^{2}} \right) }}{2}} \right) +\exp \left( {\frac{\sqrt{Na^{2}-2N}+N-2}{\tau _1 N}} \right) \cdot \frac{1}{3}\cosh ^{-1}\left( {\frac{\left( {4h^{2}} \right) +(0.56Lsd)^{2}}{d_o }} \right) },N\ge 2 \end{aligned}$$

(40)

$\tau _{1}\,\tau _{2}$ are fitting parameters describing the rate of decrement in electric flux of the neighbouring cylinders with increase in distance between them. $\tau _{1},\tau _{2}$ are taken as 2.5 and 2.0 respectively from [14]

The gate-to-gate (or) gate to source/drain capacitance (Cgtg) is taken from [14] for gate wrap around and number of walls is the independent factor for this capacitance. (The equation in [11] is taken from [10]).

$$\begin{aligned} C_{gtg} =\frac{3\kappa _2 \varepsilon _0 H_{gate} }{Lsd}+\alpha _{gtg,sr} \frac{\pi \kappa _2 \varepsilon _0 }{\ln \left( {\frac{2\pi \left( {Lsd+L_g } \right) }{2L_g +\tau _{bk} \left( {H_{gate} +h+r_O } \right) }} \right) }\nonumber \\ \end{aligned}$$

(41)

$\upalpha _{\mathrm{gtg}}$ is the factor due to screening effect of neighbouring conductors (Gate/ Source/ Drain)

$$\begin{aligned} (\alpha _{gtg} = 0.7) \end{aligned}$$

where,

$$\begin{aligned} \tau _{bk} =\hbox {exp}\left( {\frac{\left( {2-2\sqrt{1+2(}H_{gate} +L_g } \right) }{Lsd}} \right) \end{aligned}$$

(42)

The drive capacitance is calculated [11] using the following relation,

$$\begin{aligned} C=C_g L_g +f_{miller} .2\left( {C_{of}^{\left( g \right) } L_s +C_{gtg} W_{pitch} } \right) +C_{gsub}\nonumber \\ \end{aligned}$$

(43)

where,

$$\begin{aligned} \hbox {f}_{\mathrm{miller}}=1.5. \end{aligned}$$

Thus, the equations for gate wrap around transistors is taken from [14], relations for double walled channel array is taken from [11], and new device gate wrap around double walled array CNTFET is developed.

Appendix 2

For the Fig. 6, the drive current values of both the walls are projected in Fig. 5.

For Fig. 7a, b sample graph is shown in Fig. 12. The graph is for d = 2.0 nm and N = 21.

Fig. 12

Variation of drain current of DWGWA, SWGWA and their ratio with respect to drain voltage

For Fig. 8 sample graph for drive capacitance with respect to ‘k1’ is shown. The graph is for d = 2.0 nm (Fig. 13).

For Fig. 9 sample graph for drive capacitance with respect to gate length is shown. The graph is for d = 2.0 nm (Fig. 14).

For Fig. 10 sample graph for cut-off frequency is shown. The graph is for d = 2.0 nm (Fig. 15).

Fig. 13

Variation of driven capacitance with respect to k1 for DWGWA & SWGWA

Fig. 14

Driven capacitance with respect to gate length is shown. The graph is for d = 2.0 nm

Fig. 15

Variation of cut-off frequency with respect to source/drain length of DWGWA, SWGWA

For Fig. 11 sample graph for delay time is shown. The graph is for d = 2.0 nm (Fig. 16).

Fig. 16

Variation of delay time with respect to source/drain length of DWGWA, SWGWA

Fig. 17

Driven capacitance and its ratio between DWGWA and SWGWA for different gate dielectrics

Fig. 18

Driven capacitance and its ratio between DWGWA and SWGWA for different ‘h’ distance

Fig. 19

Driven capacitance and its ratio between DWGWA and SWGWA for different ‘s’ distance

Fig. 20

Driven capacitance and its ratio between DWGWA and SWGWA for different ‘Lsd’ distance

Fig. 21

Driven Capacitance and its ratio between DWGWA and SWGWA for various N

Fig. 22

Variation of Cgc of DWGWA and SWGWA with respect to number of channels

The behavior of both the devices for driven capacitance project the variations as shown in the figures from Fig. 17 to Fig. 22.