Abstract
In this paper we perform a simulation study on the limits of graphene-nanoribbon field-effect transistors (GNR-FETs) for post-CMOS digital applications. Both conventional and tunneling FET architectures are considered. Simulations of conventional narrow GNR-FETs confirm the high potential of these devices, but highlight at the same time OFF-state leakage problems due to various tunneling mechanisms, which become more severe as the width is made larger and require a careful device optimization. Such OFF-state problems are partially solved by the tunneling FETs, which allow subthreshold slopes better than 60 mV/dec, at the price of a reduced ON-current. The importance of a very good control on edge roughness is highlighted by means of a direct simulation of devices with non-ideal edges.
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Grassi, R., Gnudi, A., Gnani, E. et al. An investigation of performance limits of conventional and tunneling graphene-based transistors. J Comput Electron 8, 441–450 (2009). https://doi.org/10.1007/s10825-009-0282-2
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DOI: https://doi.org/10.1007/s10825-009-0282-2