International Journal of Parallel Programming

, Volume 41, Issue 6, pp 806–824

Extensible Recognition of Algorithmic Patterns in DSP Programs for Automatic Parallelization


  • Amin Shafiee Sarvestani
    • Department of Computer and Information ScienceLinköping University
    • Department of Computer and Information ScienceLinköping University
  • Christoph Kessler
    • Department of Computer and Information ScienceLinköping University

DOI: 10.1007/s10766-012-0229-2

Cite this article as:
Shafiee Sarvestani, A., Hansson, E. & Kessler, C. Int J Parallel Prog (2013) 41: 806. doi:10.1007/s10766-012-0229-2


We introduce an extensible knowledge based tool for idiom (pattern) recognition in DSP (digital signal processing) programs. Our tool utilizes functionality provided by the Cetus compiler infrastructure for detecting certain computation patterns that frequently occur in DSP code. We focus on recognizing patterns for for-loops and statements in their bodies as these often are the performance critical constructs in DSP applications for which replacement by highly optimized, target-specific parallel algorithms will be most profitable. For better structuring and efficiency of pattern recognition, we classify patterns by different levels of complexity such that patterns in higher levels are defined in terms of lower level patterns. The tool works statically on the intermediate representation. For better extensibility and abstraction, most of the structural part of recognition rules is specified in XML form to separate the tool implementation from the pattern specifications. Information about detected patterns will later be used for optimized code generation by local algorithm replacement e.g. for the low-power high-throughput multicore DSP architecture ePUMA.


Automatic parallelization Algorithmic pattern recognition Cetus DSP DSP code parallelization Compiler frameworks

Copyright information

© Springer Science+Business Media New York 2012