OSCI, SystemC Version 2.0 User’s Guide (2001)
http://www.archc.org, The ArchC Resource Center.
A. Fauth, J. Van Praete, and M. Freericks, Describing Instruction Set Processors using nML, In Proc. European Design and Test Conf. Paris, pp. 503–507 (March 1995), URL citeseer.nj.nec.com/fauth95describing.html.
M. R. Hartoog, J. A. Rowson, P. D. Reddy, S. Desai, D. D. Dunlop, E. A. Harcourt, and N. Khullar, Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign, In Proc. Design Automation Conference, pp. 303–306 (1997), URL citeseer.nj.nec.com/hartoog97generation.html.
V. Zivojnovic, S. Pees, and H. Meyr, LISA—Machine Description Language and Generic Machine Model for HW/SW Co-Design, Proceedings of the IEEE Workshop on VLSI Signal Processing, San Francisco (1996), URL citeseer.nj.nec.com/zivojnovic96dsp.html.
A. Hoffmann, T. Kogel, and H. Meyr, A Framework for Fast Hardware-Software Cosimulation, Proceedings of Design, Automation and Test in Europe Conference (DATE) (March 2001).
A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H. Meyr, and A. Hoffmann, A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation, Proceedings of Design and Automation Conference (DAC) (June 2002).
A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau, EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability, In Proc. European Conference on Design, Automation and Test (DATE) (March 1999).
M. Reshadi, P. Mishra, and N. Dutt, Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation, Proceedings of Design and Automation Conference (DAC) (2003).
G. Hadjiyiannis, S. Hanono, and S. Devadas, ISDL: An Instruction Set Description Language for Retargetability, Design Automation Conference (DAC), pp. 299–302 (1997), URL citeseer.nj.nec.com/hadjiyiannis97isdl.html.
G. Hadjiyiannis and S. Devadas, Techniques for Accurate Performance Evaluation in Architecture Exploration, IEEE Transactions on VLSI Systems (2002), URL citeseer.nj.nec.com/hadjiyiannis02techniques.html.
J. Hennessy and D. Patterson, Computer Organization & Design: The Hardware/Software Interface, Morgan Kaufmann (1998).
B. Cmelik and D. Keppel, Shade: A Fast Instruction-Set Simulator for Execution Profiling, ACM SIGMETRICS Performance Evaluation Review, 22(1):128–137 (May 1994), URL citeseer.nj.nec.com/article/cmelik93shade.html.
P. Viana, E. Barros, S. Rigo, R. Azevedo, and G. Araújo, Exploring Memory Hierarchy with ArchC, Proc. of the 15th Symp. on Computer Architecture and High Performance Computing, São Paulo, (SBAC-PAD’03) (November 2003).
P. Viana, E. Barros, S. Rigo, R. Azevedo, and G. Araújo, Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology, Proc. of the Design, Automation and Test in Europe (DATE’04), Paris (February 2004).
M. Reshadi, N. Bansal, P. Mishra, and N. Dutt, An Efficient Retargetable Framework for Instruction-Set Simulation, Proceedings of the 2003 International Symposium on System Synthesis (ISSS-2003), Newport Beach, California (October 2003).
C. Lee, M. Potkonjak, and W. H. Mangione-Smith, Mediabench; A Tool fo Evaluating and Synthesizing Multimedia and Communications Systems, Proc. of 30th Annual International Symposium on Microarchitecture (December 1997).
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, MiBench: A Free, Commercially Representative Embedded Benchmark Suite, IEEE 4th Annual Workshop on Workload Characterization, Austin, TX (December 2001).
S. Rigo, M. Juliato, R. Azevedo, G. Araujo and P. Centoducatte. Teaching Computer Architecture Using an Architecture Description Language, Proceedings of the Workshop on Computer Architecture Education (WCAE), held in conjunction with the International Symposium on Computer Architecture (INCA), Munich (June 2004).