Skip to main content
SpringerLink
Log in

Constructive Boolean circuits and the exactness of timed ternary simulation

  • Published:
Formal Methods in System Design Aims and scope Submit manuscript

Abstract

We classify gate level circuits with cycles based on their stabilization behavior. We define a formal class of combinational circuits, the constructive circuits, for which signals settle to a unique value in bounded time, for any input, under a simple conservative delay model, called the up-bounded non-inertial (UN) delay. Since circuits with combinational cycles can exhibit asynchronous behavior, such as non-determinism or metastability, it is crucial to ground their analysis in a formal delay model, which previous work in this area did not do.

We prove that ternary simulation, such as the practical algorithm proposed by Malik, decides the class of constructive circuits. We prove that three-valued algebra is able to maintain correct and exact stabilization information under the UN-delay model, and thus provides an adequate electrical interpretation of Malik’s algorithm, which has been missing in the literature. Previous work on combinational circuits used the upbounded inertial (UI) delay to justify ternary simulation. We show that the match is not exact and that stabilization under the UI-model, in general, cannot be decided by ternary simulation. We argue for the superiority of the UN-model for reasons of complexity, compositionality and electrical adequacy. The UN-model, in contrast to the UI-model, is consistent with the hypothesis that physical mechanisms cannot implement non-deterministic choice in bounded time.

As the corner-stone of our main results we introduce UN-Logic, an axiomatic specification language for UN-delay circuits that mediates between the real-time behavior and its abstract simulation in the ternary domain. We present a symbolic simulation calculus for circuit theories expressed in UN-logic and prove it sound and complete for the UN-model. This provides, for the first time, a correctness and exactness result for the timing analysis of cyclic circuits. Our algorithm is a timed extension of Malik’s pure ternary algorithm and closely related to the timed algorithm proposed by Riedel and Bruck, which however was not formally linked with real-time execution models.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

Notes

  1. This was called the “semantical definition” in [40].

  2. Sometimes, we also write vectors without the angled brackets, e.g., S 1 S 2⋯S m .

  3. The ternary extension can also be used, to some extent, to analyze sequential behavior (as in [8, 9, 13]).

  4. The non-determinism in the delay-model DEL accounts for low-level physical parameters which influence the signal propagation delay electrically but can neither be controlled nor kept track of by the discrete model.

  5. This is always possible if R only constrains the input.

  6. Because of the different cardinalities of \({2^{\mathbb {B}}}^{l}\) (set of regions in \(\mathbb {B}^{l}\)) and \(\mathbb {S}^{l}\) there is no way in which we could use ternary vectors to represent arbitrary binary regions in a one-to-one fashion.

  7. The term “coalesced” means that all elements \((x,y) \in \mathbb {S}\otimes \mathbb {R}^{+}_{\infty}\) in which x=⊥ or y=∞ are identified.

  8. In other words, ⊥ is treated as the completely “uninformative” truth value which is both 0 and 1 at the same time. Interestingly, the missing fourth value ⊤ for “inconsistency” arises in a dual fashion by reading ϕ≡⊤ as an abbreviation for (true⊃ϕ)∧(ϕ⊃false). Obviously, this is a contradiction and equivalent to false.

  9. Ternary algebra itself is sometimes interpreted as a logic of three truth-values in analogy to propositional logic which is the logic of two truth values. This analogy is misleading, however, as ternary algebra is not a logic. The reason is that it does not have any theorems, i.e., non-trivial ternary expressions that evaluate to “truth value” 1 under all ternary valuations.

References

  1. Backes J, Fett B, Riedel M (2008) The analysis of cyclic circuits with Boolean satisfiability. In: Proc int’l conf on computer-aided design (ICCAD’08), pp 143–148

    Google Scholar 

  2. Burch JR (1992) Delay models for verifying speed-independent asynchronous circuits. In: Proc int’l conf computer design (ICCD’92), pp 270–274

    Google Scholar 

  3. Burch JR, Dill D, Wolf E, De Micheli G (1993) Modeling hierarchical combinational circuits. In: Proc int’l conf on computer-aided design, November 1993, pp 612–617

    Google Scholar 

  4. Berry G (1999) The constructive semantics of Esterel. Draft, version 3.0, available at www.esterel.org, July 1999

    Google Scholar 

  5. Breuer MA (1972) A note on three-valued logic simulation. IEEE Trans Comput C-21(4):399–402

    Article  MathSciNet  Google Scholar 

  6. Bryant RE (1987) Boolean analysis of MOS circuits. IEEE Trans Comput-Aided 6(4):634–649

    Article  Google Scholar 

  7. Brzozowski JA, Ésik Z, Iland Y (2001) Algebras for hazard detection. In: Proc symposium on multiple-valued logic (ISMVL’01), pp 3–12

    Google Scholar 

  8. Brzozowski JA, Seger C-JH (1995) Asynchronous circuits. Springer, New York

    Book  Google Scholar 

  9. Brzozowski JA, Yoeli M (1979) On a ternary model of gate networks. IEEE Trans Comput C-28:178–184

    Article  MathSciNet  Google Scholar 

  10. Claessen K (2004) Safety property verification of cyclic synchronous circuits. In: Synchronous languages, applications, and programming SLAP 2003. ENTCS, vol 88. Elsevier, Amsterdam, pp 55–69

    Google Scholar 

  11. Davey BA, Priestley HA (2002) Introduction to lattices and order. Cambridge University Press, Cambridge

    MATH  Google Scholar 

  12. de Simone R (1996) Note: a small hardware bus arbiter specification leading naturally to correct cyclic description. Internal note: http://www-sop.inria.fr/meije/verification/esterel/doc.html

  13. Eichelberger EB (1965) Hazard detection in combinational and sequential switching circuits. IBM J Res Dev 9(2):90–99

    Article  MATH  Google Scholar 

  14. Fairtlough F, Mendler M (1997) Propositional lax logic. Inf Comput 137(1):1–33

    Article  MathSciNet  MATH  Google Scholar 

  15. Gordon MJC (1979) The denotational description of programming languages. Springer, New York

    Book  MATH  Google Scholar 

  16. Halbwachs N, Maraninchi F (1995) On the symbolic analysis of combinational loops in circuits and synchronous programs. In: Euromicro’95, September 1995, Como, Italy

    Google Scholar 

  17. Kinniment DJ (2007) Synchronization and arbitration in digital systems. Wiley, New York

    Book  Google Scholar 

  18. Kishinevski M, Kondratyev A, Taubin A, Varshavsky V (1994) Concurrent hardware: the theory and practice of self-timed design. Wiley, New York

    Google Scholar 

  19. Kleene SC (1952) Introduction to metamathematics. North Holland, Amsterdam. Chap XII, Par 64

    MATH  Google Scholar 

  20. Lamport L (2003) Arbitration-free synchronization. Distrib Comput 16(2–3):219–237

    Article  Google Scholar 

  21. Lam KC, Brayton RK (1994) Timed boolean functions. A unified formalism for exact timing analysis. Kluwer Academic, Norwell

    MATH  Google Scholar 

  22. Lloyd JW (1984) Foundations of logic programming. Springer, Berlin

    Book  MATH  Google Scholar 

  23. Malik Sharad (1994) Analysis of cyclic combinational circuits. IEEE Trans Computer-Aided Des 13(7):950–956

    Article  Google Scholar 

  24. Marino LR (1981) General theory of metastable operation. IEEE Trans Comput 30(2):107–115

    MATH  Google Scholar 

  25. Mc Geer P, Saldanha A, Brayton R, Sangiovanni-Vincentelli A (1992) Delay models and exact timing analysis. In: Sasao T (ed) New directions in logic synthesis and optimization. Kluwer, Norwell, pp 167–190

    Google Scholar 

  26. Mendler M (2000) Characterising combinational timing analyses in intuitionistic modal logic. Log J IGPL 8(6):821–853. Abstract appeared ibid. Vol 6, No 6 (Nov 1998)

    Article  MathSciNet  MATH  Google Scholar 

  27. Mendler M, Fairtlough F (1996) Ternary simulation: A refinement of binary functions or an abstraction of real-time behaviour. In: Sheeran M, Singh S (eds) Proceedings of the 3rd workshop on designing correct circuits (DCC96), October 1996. Springer, Berlin. Springer Electronic Workshops in Computing

    Google Scholar 

  28. Moggi E (1991) Notions of computation and monads. Inf Comput 93:55–92

    Article  MathSciNet  MATH  Google Scholar 

  29. Maler O, Pnueli A (1995) Timing analysis of asynchronous circuits using timed automata. In: Camurati PE, Eveking H (eds) Proceedings of the conference on correct hardware design and verification methods, Frankfurt/Main, Germany, October 1995. LNCS, vol 987, Springer, Berlin pp 189–205

    Chapter  Google Scholar 

  30. Mendler M, Shiple T, Berry G (2006) Constructive boolean circuits and the exactness of ternary simulation. Bamberger Beiträge zur Wirtschaftsinformatik und Angewandten Informatik, vol 68. University of Bamberg, August 2006

    Google Scholar 

  31. Namjoshi KS, Kurshan RP (1999) Efficient analysis of cyclic definitions. In: CAV 1999. LNCS, vol 1633, pp 394–405

    Google Scholar 

  32. Pěchouček M (1976) Anomalous response times of input synchronizers. IEEE Trans Comput 25(2):133–139

    Article  Google Scholar 

  33. Plotkin GD (1977) LCF as a programming language. Theor Comput Sci 5(3):223–256

    Article  MathSciNet  Google Scholar 

  34. Riedel M, Bruck J (2003) Cyclic combinational circuits: Analysis for synthesis. In: Int’l workshop on logic synthesis

    Google Scholar 

  35. Riedel MD, Bruck J (2003) The synthesis of cyclic combinational circuits. In: DAC, June 2003. ACM, New York

    Google Scholar 

  36. Riedel MD, Bruck J (2004) Timing analysis of cyclic combinational circuits. In: Int’l workshop on logic and synthesis, Temecula Creek, CA

    Google Scholar 

  37. Shiple TR, Brayton RK, Berry G, Sangiovanni-Vincentelli AL (2002) Logical analysis of combinational cycles. Technical Report UCB/ERL M02/21, EECS Department, University of California, Berkeley. This is a revision of selected parts of Shiple’s PhD thesis [41]

  38. Schneider K, Brandt J, Schuele T (2004) Causality analysis of synchronous programs with delayed actions. In: Conference on compilers, architecture, and synthesis for embedded systems, (CASES), Washington DC, USA, September 2004. ACM, New York, pp 179–189

    Google Scholar 

  39. Schneider K, Brandt J, Schuele T, Tuerk T (2005) Maximal causality analysis. In: Conference on application of concurrency to system design (ACSD), St Malo, France, June 2005. IEEE Comput Soc, Los Alamitos, pp 106–115

    Chapter  Google Scholar 

  40. Shiple TR, Berry G, Touati H (1996) Constructive analysis of cyclic circuits. In: Proc European design and test conference, March 1996, pp 328–333

    Chapter  Google Scholar 

  41. Shiple TR (1996) Formal analysis of synchronous circuits. PhD thesis, UC Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, October 1996. Memorandum No. UCB/ERL M96/76

  42. Marques Silva JPM, Sakallah KA (1993) An analysis of path sensitization criteria. In: Proc ICCD’93, pp 68–72

    Google Scholar 

  43. Srinivasan A, Malik S (1996) Practical analysis of cyclic combinational circuits. In: IEEE custom integrated circuits conference, pp 381–384

    Google Scholar 

  44. Stephan PR, Brayton RK (1993) Physically realizable gate models. In: Proc ICCD’93, pp 442–445

    Google Scholar 

  45. Stok Leon (1992) False loops through resource sharing. In: Proc int’l conf on computer-aided design, November 1992, pp 345–348

    Google Scholar 

  46. Tarski A (1955) A lattice-theoretical fixedpoint theorem and its applications. Pac J Math 5:285–309

    MathSciNet  MATH  Google Scholar 

  47. Unger SH (1969) Asynchronous sequential switching circuits. Wiley Interscience, New York

    Google Scholar 

  48. Unger SH (1995) Hazards, critical races, and metastability. IEEE Trans Comput 44(6):754–768

    Article  MATH  Google Scholar 

  49. Watanabe Y, Brayton RK (1993) The maximum set of permissible behaviors for FSM networks. In: Proc int’l conf on computer-aided design, November 1993, pp 316–320

    Google Scholar 

  50. Yoeli M, Brzozowski JA (1977) Ternary simulation of binary gate networks. In: Dunn JM, Epstein G (eds) Modern uses of multiple-valued logic. Reidel, Dordrecht, pp 41–50

    Google Scholar 

  51. Yoeli M, Rinon S (1964) Application of ternary algebra to the study of static hazards. J ACM 11:84–97

    Article  MATH  Google Scholar 

Download references

Acknowledgements

We are grateful to the anonymous reviewers for their suggestions to improve this article. The first author was supported by the European Community as a member of the TYPES Project FP6-IST-510996 and the German Research Foundation DFG through the project grant “Precision-timed Synchronous Processing (PRETSY)”.

Author information

Authors and Affiliations

  1. Faculty of Information Systems and Applied Computer Sciences, The Otto-Friedrich University of Bamberg, Bamberg, Germany

    Michael Mendler

  2. Synopsys, Inc., Mountain View, CA, USA

    Thomas R. Shiple

  3. INRIA, Sophia Antipolis, France

    Gérard Berry

Authors
  1. Michael Mendler
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Thomas R. Shiple
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Gérard Berry
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Michael Mendler.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Mendler, M., Shiple, T.R. & Berry, G. Constructive Boolean circuits and the exactness of timed ternary simulation. Form Methods Syst Des 40, 283–329 (2012). https://doi.org/10.1007/s10703-012-0144-6

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10703-012-0144-6

Keywords

Search

Navigation