Abdulla PA, Bjesse P, Een N (2000) Symbolic reachability analysis based on SAT-solvers. In: Proceedings of the 6th international conference on tools and algorithms for the construction and analysis of systems (TACAS’2000). LNCS, vol 1785. Springer, Berlin
CrossRefAmla N, Du X, Kuehlmann A, Kurshan RP, McMillan KL (2005) An analysis of SAT-based model checking techniques in an industrial environment. In: Conference on correct hardware design and verification methods (CHARME’05)). LNCS, vol 3725. Springer, Berlin
CrossRefBaumgartner J, Sheeran M (eds) (2007) Int. conf. on formal methods in computer-aided design (FMCAD’07). IEEE, New York
Bentley B (2005) Validating a modern microprocessor, invited talk. In: 17th international conference on computer aided verification (CAV’05). LNS, vol 3576. Springer, Berlin. Slides available at
http://www.cav2005.inf.ed.ac.uk/Fbentley_CAV_07_08_2005.ppt
Biere A (2007a) PicoSAT ver 535, system description for the SAT competition. Available at
http://www.satcompetition.org/2007/picosat.pdf
Biere A (2007b) Short history on SAT solver technology and what is next? Invited talk. In: Int. conf. on theory and applications of satisfiability testing (SAT’07). Slides available at
http://fmv.jku.at/biere/talks/Biere-SAT07-talk.pdf
Biere A, Cimatti A, Clarke EM, Zhu Y (1999a) Symbolic model checking without BDDs. In: 5th international conference on tools and algorithms for construction and analysis of systems (TACAS’99). LNCS, vol 1579. Springer, Berlin
CrossRefBiere A, Clarke E, Raimi R, Zhu Y (1999b) Verifying safety properties of a powerPC microprocessor using symbolic model checking without BDDs. In: Int. conf. on computer aided verification (CAV’99). LNCS, vol 1633. Springer, Berlin
CrossRefBiere A, Cimatti A, Clarke E, Strichman O, Zhu Y (2003) Bounded model checking. In: Advances in computers
Bjesse P, Claessen K (2000) SAT-based verification without state space traversal. In: Formal methods in computer-aided design (FMCAD’00). LNCS, vol 1954. Springer, New York, pp 372–389
CrossRefBjesse P, Leonard T, Mokkedem A (2001) Finding bugs in an alpha microprocessor using satisfiability solvers. In: Int. conf. on computer aided verification (CAV’01). LNCS, vol 2102. Springer, New York
Borälv A, Stålmarck G (1998) Prover technology in railways. In: Industrial-strength formal methods. Academic, London
Bradley A, Manna Z (2007) Checking safety by inductive generalization of counterexamples to induction. In: Int. conf. on formal methods in computer-aided design (FMCAD’07). IEEE, New York
Bryant R (1986) Graph-based algorithms for boolean function manipulation. IEEE Trans. Comp. c-35:8
Bryant RE, Kukula JH (2002) Formal methods for functional verification. In: Best of ICCAD: 20 years of excellence in computer-aided design. ACM, New York
Case M, Mishchenko A, Brayton R (2007) Automated extraction of inductive invariants to aid model checking. In: Int. conf. on formal methods in computer-aided design (FMCAD’07). IEEE, New York
Cassandras CG, Lafortune S (2007) Introduction to discrete event systems. Springer, Berlin
Chauhan P, Kroening D, Clarke E (2004) A SAT-based algorithm for reparameterization in symbolic simulation. In: Design automation conference (DAC’04). ACM, New York
Cimatti A (2008) Beyond boolean SAT: satisfiability modulo theories. In: Proceedings of the 9th international workshop on discrete event systems. WODES08, pp 68–73
Claessen K, Een N, Sheeran M, Sörensson N (2008) SAT-solving in practice. In: Invited paper in session on SAT in WODES08
Clarke EM, Grumberg O, Peled DA (2000) Model checking. MIT, Cambridge
Cook S (1971) The complexity of theorem-proving procedures. In: Proc. 3rd ACM symp. on the theory of computing. ACM, New York
Copty F, Fix L, Fraer R, Giunchiglia E, Kamhi G, Tacchella A, Vardi MY (2001) Benefits of bounded model checking at an industrial setting. In: Int. conf. on computer aided verification (CAV’01). LNCS, vol 2102. Springer, Berlin
Davis M, Putnam H (1960) A computing procedure for quantification theory. J ACM 7:201–215 (reprinted in Siekman and Wrightson 1983)
MATHCrossRefMathSciNetDavis M, Logemann G, Loveland D (1962) A machine program for theorem proving. Commun ACM 5:394–397 (reprinted in Siekman and Wrightson 1983)
MATHCrossRefMathSciNetEen N (1999) Symbolic reachability analysis based on SAT-solvers. Master’s thesis, Department of Computer Systems, Uppsala University, Sweden
Een N (2007) Practical SAT, invited tutorial at int. conf. on formal methods in computer aided design. Slides available at
http://minisat.se/Papers.html
Een N, Biere A (2005) Effective preprocessing in SAT through variable and clause elimination. In: 8th int. conf. theory and applications of satisfiability testing (SAT’05). LNCS, vol 3569. Springer, New York
Een N, Sörensson N (2003a) An extensible SAT solver. In: Proc. of theory and applications of satisfiability testing (SAT’03). LNCS, vol 2919. Springer, New York
Een N, Sörensson N (2003b) Temporal induction by incremental SAT solving. In: First int. workshop on bounded model checking. ENTCS, vol 89, no 4
Een N, Sörensson N (2005) MiniSat v1.13 - a SAT solver with conflict-clause minimization, system description for the SAT competition. Available at
http://minisat.se/Papers.html
Een N, Mishchenko A, Sörensson N (2007) Applying logic synthesis for speeding up SAT. In: Int. conf. on theory and applications of satisfiability testing (SAT’07). LNCS, vol 4501. Springer, New York
CrossRefGoldberg E, Novikov Y (2002) BerkMin: a fast and robust SAT solver. In: Design and test in Europe (DATE’02). IEEE Computer Society, Los Alamitos
Huang J (2007) The effect of restarts on the efficiency of clause learning. In: IJCAI, pp 2318–2323
Groote JF, van Vlijmen SFM, Koorn JWC (1995) The safety guaranteeing system at station hoorn-kersenboogerd (extended abstract). In: Proc. 10th annual conference on computer assurance (COMPASS’95). IEEE, New York, pp 57–68
Guerra e Silva L, Marques-Silva JP, Silveira LM, Sakallah KA (1998) Timing analysis using propositional satisfiability. In: IEEE international conference on electronics, circuits and systems (ICECS). IEEE, New York
Kautz H, Selman B (1992) Planning as Satisfiability. In: Proceedings ECAI-92. Wiley, New York
Kunz W (2007) Formal verification of systems-on-chip—industrial experiences and scientific perspectives. Invited talk at int. conf. on formal methods in computer aided design. Slides available at
http://www.fmcad.org/2007 (under Advance Program)
Kunz W, Pradhan D (1994) Recursive learning: a new implication technique for efficient solutions to CAD-problems: test, verification and optimization. IEEE Trans Comput-Aided Des 13(9): 1149–1158
CrossRefLarrabee T (1992) Test pattern generation using boolean satisfiability. IEEE Trans Comput-Aided Des 11(1):6–22
CrossRefLuby M, Sinclair A, Zuckerman D (1993) Optimal speedup of Las Vegas algorithms. In: Israel symposium on theory of computing systems, pp 128–133.
citeseer.ist.psu.edu/article/luby93optimal.html
Marques-Silva J (2008) Practical applications of boolean satisfiability. In: Proceedings of the 9th international workshop on discrete event systems. WODES08, pp 74–80
Marques-Silva J, Sakallah K (1996) GRASP: A new search algorithm for satisfiability. In: International conference on computer-aided design (ICCAD’96). IEEE, New York, pp 220–227
CrossRefMarques-Silva J, Sakallah K (1997) Robust search algorithms for test pattern generation. In: Fault-tolerant computing symposium (FTCS). IEEE Computer Society, Los Alamitos
McMillan KL (2003) Interpolation and SAT-based model checking. In: Int. conf. on computer aided verification (CAV’03). LNCS, vol 2725. Springer, New York
Mony H, Baumgartner J, Paruthi V, Kanzelman R, Kuehlmann A (2004) Scalable Automated verification via expert-system guided transformations. In: International conference on formal methods in computer-aided design (FMCAD’04). LNCS, vol 3312. Springer, New York
Moskewicz M, Madigan C, Zhao Y, Zhang L, Malik S (2001) Chaff: engineering an efficient SAT solver. In: Design automation conf. (DAC’01). IEEE, New York
Nam GJ, Sakallah KA, Rutenbar RA (1999) Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based boolean SAT. In: International symposium on field programmable gate arrays. ACM, New York
Pipatsrisawat K, Darwiche A (2007) A lightweight component caching scheme for satisfiability solvers. In: Marques-Silva J, Sakallah KA (eds) Int. conf. on theory and applications of satisfiability testing (SAT’07). LNCS, vol 4501. Springer, New York, pp 294–299
CrossRefPrasad M, Biere A, Gupta A (2005) A survey of recent advances in SAT-based formal verification. In: Intl. journal on software tools for technology transfer (STTT), vol 7, no 2
Ramadge PJ, Wonham WM (1987) Supervisory control of a class of discrete event processes. SIAM J Control Optim 25(1):206–230
MATHCrossRefMathSciNetRamadge PJG, Wonham WM (1989) The control of discrete event systems. Proc IEEE 77(1):81–98
CrossRefSäflund M (1994) Modelling and formally verifying systems and software in industrial applications. In: Second int. conf. on reliability, maintainability and safety (ICRMS ’94). International Academic, London
Shacham O, Zarpas E (2003) Tuning the VSIDS decision heuristic for bounded model checking. In: Proc. fourth international workshop on microprocessor test and verification, common challenges and solutions (MTV 2003). IEEE Computer Society, Los Alamitos
Sheeran M, Stålmarck G (2000) A tutorial on Stålmarck’s proof procedure for propositional logic. Form Methods Syst Des 16(1):23–58
CrossRefSheeran M, Singh S, Stålmarck G (2000) Checking safety properties using induction and a SAT-solver. In: Formal methods in computer-aided design (FMCAD’00). LNCS, vol 1954. Springer, New York, pp 108–125
CrossRefSiekman J, Wrightson G (eds) (1983) Automation of reasoning. Springer, New York
Srivas M, Camilleri A (eds) (1996) Int. conf. on formal methods in computer-aided design. LNCS, vol 1146. Springer, New York
Stålmarck G (1989) A system for determining propositional logic theorems by applying values and rules to triplets that are generated from a formula. Swedish patent no. 467 076 (approved 1992), U.S. patent no. 5 276 897 (approved 1994), European patent no. 0403 454 (approved 1995)
Tseitin G (1968) On the complexity of derivation in propositional calculus. In: Studies in constr. math. and math. logic
van Eijk C (1998) Sequential equivalence checking without state space traversal. In: Int. conf. on design automation and test in Europe (DATE’98). IEEE Computer Society, Los Alamitos
Voronov A, Åkesson K (2008) Supervisory control using satisfiability solvers. In: Proceedings of the 9th international workshop on discrete event systems. WODES08, pp 81–86
Zhang H (1997) Sato: an efficient propositional prover. In: International conference on automated deduction, CADE-14. LNCS, vol 1249. Springer, New York, pp 272–275