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Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

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Abstract

Using dynamic partial reconfiguration (DPR), several circuits can be time-multiplexed on the same FPGA region, saving considerable area compared to an implementation without DPR. However, the long reconfiguration time to switch between circuits remains a significant problem. In this work we show that it is possible to significantly reduce this overhead when the number of circuits is limited. We lower the DPR overhead by reducing the number of configuration bits that needs to be reconfigured. This is achieved by keeping a (predetermined) part of the configuration frames of the DPR region constant/static for all circuits and, consequentially, sharing this part of the configuration between all the circuits. We show that this can be done maintaining the possibility to implement completely unrelated circuits in the DPR region. An extension of the Pathfinder algorithm, called StaticRoute, is presented. It is able to route the nets of the different circuits simultaneously in such a way that the routing of the different circuits is the same in the static part and may only differ in the dynamic part. Our approach is evaluated on the architecture of a commercially available SRAM-based FPGA. We explore how the static part in the configuration memory is best chosen and investigate the associated impact on maximum operating clock frequency as the number of circuits increases. Our experiments show that it is possible to make 50 % of the routing configuration static and therefore reduce the routing reconfiguration time by 50 %, without a significant impact on maximum clock frequency of the circuits. This corresponds to a reduction of total reconfiguration time of 34 %.

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Notes

  1. This is a simplification. The nodes can also represent logical pins or sources or sinks. These are treated in the same way [10].

References

  1. Bleeding edge threats website. http://www.bleedingthreats.net

  2. Abouelella F, Davidson T, Meeus W, Bruneel K, Stroobandt D (2013) How to efficiently implement dynamic circuit specialization systems. ACM Trans Des Autom Electron Syst 38

  3. Al Farisi B, Bruneel K, Cardoso JMP, Stroobandt D (2013) An automatic tool flow for the combined implementation of multi-mode circuits. In: Proceedings of the design, automation, and test in Europe conference and exhibition, Grenoble, France, pp 821–826

  4. Al Farisi B, Bruneel K, Stroobandt D Staticroute: A novel router for the dynamic partial reconfiguration of fpgas (2013) In: 23rd IEEE international conference on field programmable logic and applications (FPL), IEEE, pp 1–7

  5. Al Farisi B, Heyse K, Bruneel K, Stroobandt D (2011) Memory-efficient and fast run-time reconfiguration of regularly structured designs. In: 21st International conference on field programmable logic and applications, Chania, Crete, Greece, pp 171–176

  6. Al Farisi B, Vansteenkiste E, Bruneel K, Stroobandt D (2013) A novel tool flow for increased routing configuration similarity in multi-mode circuits. In: Proceedings of IEEE computer society annual symposium on VLSI 2013 (ISVLSI13), Natal, Brazil, pp 96–101

  7. Altera (2012) Engineering change management with the chip planner

  8. Altera (2014) Stratix IV device handbook. http://www.altera.com/literature/hb/stratix-iv/stx4_5v4.pdf

  9. Becker T, Koester M, Luk W (2010) Automated placement of reconfigurable regions for relocatable modules. In: Proceedings of 2010 IEEE international symposium on circuits and systems (ISCAS), IEEE, pp 3341–3344

  10. Betz V, Rose J, Marquardt A (eds) (1999) Architecture and CAD for deep-submicron FPGAs. Kluwer Academic Publishers, Norwell

    Google Scholar 

  11. Chavet C, Andriamisaina C, Coussy P, Casseau E, Juin E, Urard P, Martin E (2007) A design flow dedicated to multi-mode architectures for dsp applications. In: IEEE/ACM international conference on computer-aided design, 2007 (ICCAD 2007), IEEE, pp 604–611

  12. Chen W, Wang Y, Wang X, Peng C (2008) A new placement approach to minimizing FPGA reconfiguration data. In: International conference on embedded software and systems ICESS’08, IEEE, pp 169–174

  13. Claus C, Ahmed R, Altenried F, Stechele W (2010) Towards rapid dynamic partial reconfiguration in video-based driver assistance systems. In: Reconfigurable computing: architectures, tools and applications, Springer, pp 55–67

  14. Compton K, Hauck S (2002) Reconfigurable computing: a survey of systems and software. ACM Comput Surv (CSUR) 34(2):171–210

    Article  Google Scholar 

  15. Cordone R, Redaelli F, Redaelli MA, Santambrogio MD, Sciuto D (2009) Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs. IEEE Trans Comput Aided Des Integr Circuits Syst 28(5):662–675

    Article  Google Scholar 

  16. Coussy P, Lhairech-Lebreton G, Heller D, Martin E (2010) Gaut-a free and open source high-level synthesis tool. In: IEEE design automation and test in Europe-university booth

  17. Della Torre M, Malik U, Diessel O (2005) A configuration system architecture supporting bit-stream compression for FPGAs. In: Advances in computer systems architecture, Springer, pp 415–428

  18. Diessel O, ElGindy H, Middendorf M, Schmeck H, Schmidt B (2000) Dynamic scheduling of tasks on partially reconfigurable FPGAs. In: IEE Proceedings computers and digital techniques, vol. 147, IET, pp 181–188

  19. Duhem F, Muller F, Lorenzini P (2011) Farm: fast reconfiguration manager for reducing reconfiguration time overhead on FPGA. In: Reconfigurable computing: architectures, tools and applications, Springer, pp 253–260

  20. Eto E (2003) Difference-based partial reconfiguration

  21. Hansen SG, Koch D, Torresen J High speed partial run-time reconfiguration using enhanced ICAP hard macro. In: IEEE international symposium on parallel and distributed processing workshops and Phd forum (IPDPSW), IEEE, pp 174–180

  22. Hariyama M, Muthumala WH, Kameyama M (2006) Dynamically reconfigurable gate array based on fine-grained switch elements and its CAD environment. In: IEEE Asian solid-state circuits conference, 2006 (ASSCC 2006), IEEE, pp 155–158

  23. Heyse K, Al Farisi B, Bruneel K, Stroobandt D (2012) Automating reconfiguration chain generation for SRL-based run-time reconfiguration. In: Lectue notes in computer science, vol. 7199, Springer, Berlin, Germany, pp 1–12

  24. Hubner M, Gohringer D, Noguera J, Becker J (2010) Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. In: IEEE international symposium on parallel & distributed processing, Workshops and Phd forum (IPDPSW), IEEE, pp 1–8

  25. Kalte H, Lee G, Porrmann M, Ruckert U (2005) Replica: a bitstream manipulation filter for module relocation in partial reconfigurable systems. In: Proceedings of the 19th IEEE international symposium on parallel and distributed processing, IEEE, p 151b

  26. Koch D, Beckhoff C, Teich J (2009) Minimizing internal fragmentation by fine-grained two-dimensional module placement for runtime reconfiguralble systems. In: 17th IEEE symposium on field programmable custom computing machines, FCCM’09, IEEE, pp 251–254

  27. Lavin C, Padilla M, Lamprecht J, Lundrigan P, Nelson B, Hutchings B (2011) Rapidsmith: do-it-yourself CAD tools for Xilinx FPGAs. In: International conference on field programmable logic and applications (FPL), IEEE, pp 349–355

  28. Lemieux G, Lee E, Tom M, Yu A (2004) Directional and single-driver wires in FPGA interconnect. In: IEEE international conference on field-programmable technology, IEEE, pp 41–48

  29. Lewis D, Ahmed E, Baeckler G, Betz V, Bourgeault M, Cashman D, Galloway D, Hutton M, Lane C, Lee A et al (2005) The Stratix II logic and routing architecture. In: Proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays, ACM, pp 14–20

  30. Li Z, Hauck S (2002) Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. In: Proceedings of the 2002 ACM/SIGDA tenth international symposium on field-programmable gate arrays, ACM, pp 187–195

  31. Lindholm JV, McEwen IL, Young JT (2006) Routing with frame awareness to minimize device programming time and test cost. US Patent 7,149,997

  32. Luu J, Rose J (2012) VPR 6.0 user manual. vtr-verilog-to-routing.googlecode.com/files/VPR\_User\_Manual\_6.0.pdf

  33. Manet P, Maufroid D, Tosi L, Gailliard G, Mulertt O, Di Ciano M, Legat JD, Aulagnier D, Gamrat C, Liberati R et al (2008) An evaluation of dynamic partial reconfiguration for signal and image processing in professional electronics applications. EURASIP J Embedded Syst 2008:1

    Google Scholar 

  34. Marconi T, Hur JY, Bertels K, Gaydadjiev G (2010) A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. In: IEEE 8th symposium on application specific processors (SASP), 2010, IEEE, pp 87–92

  35. Masud M, Wilton S (1999) A new switch block for segmented fpgas. In: Lysaght P, Irvine J, Hartenstein R (eds) Field programmable logic and applications, vol 1673., Lecture notes in computer scienceSpringer, Berlin, pp 274–281

    Chapter  Google Scholar 

  36. McMurchie L, Ebeling C (1995) Pathfinder: a negotiation-based performance-driven router for FPGAs. In: Proceedings of the 1995 ACM third international symposium on field-programmable gate arrays, ACM, pp 111–117

  37. Nava F, Sciuto D, Santambrogio MD, Herbrechtsmeier S, Porrmann M, Witkowski U, Rueckert U (2011) Applying dynamic reconfiguration in the mobile robotics domain: a case study on computer vision algorithms. ACM Trans Reconfigurable Technol Syst 4(3):29:1–29:22

    Article  Google Scholar 

  38. Papadimitriou K, Dollas A, Hauck S (2011) Performance of partial reconfiguration in FPGA systems: a survey and a cost model. ACM Trans Reconfigurable Technol Syst 4(4):36:1–36:24

    Article  Google Scholar 

  39. Prasad Raghuraman K, Wang H, Tragoudas S (2005) A novel approach to minimizing reconfiguration cost for lut-based FPGAs. In: 18th international conference on VLSI design, IEEE, pp 673–676

  40. Raghuraman K, Wang H, Tragoudas S (2006) Minimizing FPGA reconfiguration data at logic level. In: Proceedings of the 7th international symposium on quality electronic design, IEEE Computer Society, pp 219–224

  41. Rose J, Luu J, Yu CW, Densmore O, Goeders J, Somerville A, Kent KB, Jamieson P, Anderson J (2012) The VTR project: architecture and CAD for FPGAs from verilog to routing. In: Proceedings of FPGA, ACM, pp 77–86

  42. Rousseau B, Manet P, Delavallée T, Loiselle I, Legat JD (2012) Dynamically reconfigurable architectures for software-defined radio in professional electronic applications. In: Design technology for heterogeneous embedded systems, Springer, pp 437–455

  43. Rullmann M, Merker R (2006) Maximum edge matching for reconfigurable computing. In: 20th International parallel and distributed processing symposium, 2006 (IPDPS 2006), IEEE

  44. Sedcole P, Blodget B, Becker T, Anderson J, Lysaght P (2006) Modular dynamic reconfiguration in Virtex FPGAs. Comput Digital Tech 153(3):157–164

    Article  Google Scholar 

  45. Shang L, Jha NK (2002) Hardware–software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs. In: Proceedings of the 2002 Asia and South Pacific design automation conference, IEEE Computer Society, p 345

  46. Smith AM, Constantinides GA, Cheung PY (2009) Area estimation and optimisation of FPGA routing fabrics. In: International conference on field programmable logic and applications FPL 2009, IEEE, pp 256–261

  47. Sourdis I, Bispo J, Cardoso J, Vassiliadis S (2008) Regular expression matching in reconfigurable hardware. J Signal Process Syst 51:99–121

    Article  Google Scholar 

  48. Tan H, DeMara RF (2006) A physical resource management approach to minimizing FPGA partial reconfiguration overhead. In: IEEE international conference on reconfigurable computing and FPGA’s, 2006 (ReConFig 2006), IEEE, pp 1–5

  49. Trimberger S (1998) Scheduling designs into a time-multiplexed fpga. In: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, ACM, pp 153–160

  50. Trimberger S, Carberry D, Johnson A, Wong J (1997) A time-multiplexed FPGA. In: Proceedings of the 5th annual IEEE symposium on field-programmable custom computing machines, 1997, IEEE, pp 22–28

  51. Vipin K, Fahmy SA (2012) A high speed open source controller for FPGA partial reconfiguration. In: International conference on field-programmable technology (FPT), IEEE, pp 61–66

  52. Xilinx (2012) UG191(v3.11): Virtex-5 FPGA user guide. Xilinx

  53. Yang S (1991) Logic synthesis and optimization benchmarks user guide: version 3.0. Citeseer

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Acknowledgments

Brahim Al Farisi is sponsored by IWT, Agency for Innovation through Science and Technology in Flanders. Karel Heyse is supported by a Ph.D. grant of the Flemish Fund for Scientific Research (FWO – Vlaanderen).

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Al Farisi, B., Heyse, K., Bruneel, K. et al. Enabling FPGA routing configuration sharing in dynamic partial reconfiguration. Des Autom Embed Syst 19, 189–221 (2015). https://doi.org/10.1007/s10617-014-9143-8

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