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Architecture-aware configuration and scheduling of matrix multiplication on asymmetric multicore processors

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Abstract

Asymmetric multicore processors have recently emerged as an appealing technology for severely energy-constrained environments, especially in mobile appliances where heterogeneity in applications is mainstream. In addition, given the growing interest for low-power high performance computing, this type of architectures is also being investigated as a means to improve the throughput-per-Watt of complex scientific applications on clusters of commodity systems-on-chip. In this paper, we design and embed several architecture-aware optimizations into a multi-threaded general matrix multiplication (gemm), a key operation of the BLAS, in order to obtain a high performance implementation for ARM big.LITTLE AMPs. Our solution is based on the reference implementation of gemm in the BLIS library, and integrates a cache-aware configuration as well as asymmetric-static and dynamic scheduling strategies that carefully tune and distribute the operation’s micro-kernels among the big and LITTLE cores of the target processor. The experimental results on a Samsung Exynos 5422, a system-on-chip with ARM Cortex-A15 and Cortex-A7 clusters that implements the big.LITTLE model, expose that our cache-aware versions of gemm with asymmetric scheduling attain important gains in performance with respect to its architecture-oblivious counterparts while exploiting all the resources of the AMP to deliver considerable energy efficiency.

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Notes

  1. According to this definition, servers equipped with one (or more) general-purpose multicore processor(s) and a PCIe-attached graphics accelerator, or systems-on-chip like the NVIDIA Tegra TK1, are excluded from this category.

  2. An ARM cluster, in the company’s official terminology, can be viewed as a NUMA island or socket, and should not be confused with a parallel system with distributed memory.

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Acknowledgments

The researchers from Universitat Jaume I were supported by projects CICYT TIN2011-23283 and TIN2014-53495-R of MINECO and FEDER, the EU project FP7 318793 “EXA2GREEN” and the FPU program of MECD. The researcher from Universidad Complutense de Madrid was supported by project CICYT TIN2012-32180.

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Authors and Affiliations

  1. Depto. Ingeniería y Ciencia de Computadores, Universidad Jaume I, Avda. Sos Baynat s/n, 12071, Castellón de la plana, Spain

    Sandra Catalán, Rafael Mayo, Rafael Rodríguez-Sánchez & Enrique S. Quintana-Ortí

  2. Depto. de Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, Madrid, Spain

    Francisco D. Igual

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  1. Sandra Catalán
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  2. Francisco D. Igual
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Correspondence to Rafael Rodríguez-Sánchez.

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Catalán, S., Igual, F.D., Mayo, R. et al. Architecture-aware configuration and scheduling of matrix multiplication on asymmetric multicore processors. Cluster Comput 19, 1037–1051 (2016). https://doi.org/10.1007/s10586-016-0611-8

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