Abstract
This paper considers a method for executing arithmetic addition and multiplication operations in the Galois basis. A basic adder structure is developed that increases the speed of executing arithmetic operations over Galois codes and implements the functional structure of a special-purpose processor based on the vertical information technology.
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References
Chiou-Yng Lee, Pramod Kumar Meher, Che Wun Chiou, and Jim-Min Lin, “Concurrent detection/correction in finite field architectures over GF (2m),” in: Cryptography Research Perspectives, Nova Sci. Publ., New York (2008), pp. 49–96.
Ya. M. Nykolaychuk, Galois Field Codes: Theory and Application [in Russian], TZOO “Ternograf,” Ternopil (2012).
Ya. M. Nykolaychuk, Theory of Information Sources [in Russian], TZOO “Ternograf,” Ternopil (2010).
Shunsuke Kamijo, “Galois field arithmetic processor,” U.S. Patent No. 6,523,054 (Feb. 18, 2003).
Kentaro Odaka, “Processing circuit for operating on elements of a Galois field,” U.S. Patent No. 4, 473,887 (Sep, 25, 1984).
Yosi Stein, Haim Primo, and Yaniv Sapir, “Galois field multiply/multiply-add/multiply accumulate,” U.S. Patent No. 7,082,452 (Jul. 25, 2006).
Michito Matsumoto and Kazuhiro Murase, “Multiplier in a Galois field,” U.S. Patent No. 4,918,638 (Apr. 17, 1990).
Ya. M. Nykolaychuk, O. M. Zastavnyy, and P. V. Humennij, “Theoretical bases and principles of construction of an arithmetic logic unit on the basis of the vertical information technology,” Vestn. Khmeln. Nats. Un-ta, No. 2, 190–196 (2012).
P. V. Humennij, “Structure and system characteristics of multiport JBOD based on the vertical information technology in the Galois basis,” Selected Works of the Buchach Institute of Management and Audit, 1, No. 6, 71–75 (2010).
V. S. Glukhov and M. V. Nogal, “A specialized one-bit processor for information protection in guaranteedly stable systems,” Radioelectronic and Computer Systems, 104–109 (2008).
A. Drozd and S. Antoshchuk, “New on-line testing methods for approximate data processing in computing circuits,” in: Proc. 6th IEEE Intern. Conf. on Intellig. Data Acquisition and Adv. Comput. Syst.: Technology and Applications, Prague (2011), pp. 291–294.
I. V. Sergienko, A. M. Gupal, and A. A. Vagis, “Complementarity relations in encoding bases along one thread in DNA chromosomes,” Problems of Control and Informatics, No. 4, 153–157 (2005).
C. W. Chiou, Chiou-Yng Lee, An-Wen Deng, and Jim-Min Lin, “Concurrent error detection in Montgomery multiplication over GF (2m),” IEICE Trans. on Fundamentals, E89-A, No. 2, 566–574 (2006).
H. Fan, “New GF (2n) parallel multiplier using redundant representation. Researches in GF (2n),” Multiplication Algorithms, PhD Dissertation [in Chinese], Tsinghua Univ., http://eprint.iarc.org/2004/137.
J.-W. Lee, P.K. Meher, and J. C. Patra, “Concurrent error detection in bit-serial normal basis multiplication over GF (2m). Using Multiple Parity Prediction Schemes in Large Scale Integration (VLSI) Systems,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems (2009).
Ya. M. Nykolaychuk and P. V. Humennij, “Analog-digital transformer,” Inventor’s Certificate No. 70744 U Ukraine H038M, Bul. No. 12 (2012).
N. D. Krutskevich and Ya. M. Nykolaychuk, “Principles of construction of an RCG processor,” in: Proc. Intern. Sci.-Techn. Conf. “Monitoring and Control in Complex Systems (MCCS-2003),” UNIVERSUM-Vinnytsia, Vinnytsia (2003).
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Translated from Kibernetika i Sistemnyi Analiz, No. 3, pp. 17–26, May–June, 2014.
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Nykolaychuk, Y.M., Humennij, P.V. Theoretical Bases, Methods, and Processors for Transforming Information in Galois Field Codes on the Basis of the Vertical Information Technology. Cybern Syst Anal 50, 338–347 (2014). https://doi.org/10.1007/s10559-014-9622-8
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DOI: https://doi.org/10.1007/s10559-014-9622-8