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CMOS substrate coupling modeling and analysis flow for submicron SoC design

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Abstract

CMOS technology substrate crosstalk modeling and a respective analysis flow that captures the affected circuit performance is described. The proposed methodology can be seamlessly integrated into any industrial Analog/RF circuit design flow, and be compatible within standard design environments. It provides accurate estimation of the substrate coupling effects and can estimate adequately all the mask design level isolation performance trends by adapting an advanced substrate modeling concept based on geometrical and process data. Different substrate model accuracy constraints can be invoked depending on the design phase and the simulation time needs. The provided accuracy is validated by correlating simulation results versus on wafer silicon measurements in a 28 nm CMOS set of ring oscillators with carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV while the error sigma is 765 μV.

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Acknowledgements

The contribution of Hui Zhang, Antonius Koller and Reinhard Golly of INTEL—Mobile Communications Group—RFAD Characterization Laboratory, during the silicon measurements, is greatly appreciated.

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Authors and Affiliations

  1. Electronics Lab., Department of Physics, Aristotle University of Thessaloniki, Thessaloníki, 54124, Greece

    T. Noulis

  2. Intel Germany GmbH (Intel Corporation), Am Campeon 10, 85579, Neubiberg, Germany

    P. Baumgartner

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  1. T. Noulis
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  2. P. Baumgartner
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Correspondence to T. Noulis.

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Noulis, T., Baumgartner, P. CMOS substrate coupling modeling and analysis flow for submicron SoC design. Analog Integr Circ Sig Process 90, 477–485 (2017). https://doi.org/10.1007/s10470-016-0883-1

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  • DOI: https://doi.org/10.1007/s10470-016-0883-1

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