Abstract
The evolution of technology into deep sub-micron domains leads to increasingly complex timing closure problems to design multiprocessor systems. One natural alternative is to resort to the globally asynchronous, locally synchronous paradigm. This work proposes a generic architecture for very low power- and area-overhead local clock generators (LCGs) to drive processors, network-on-chip routers and other intellectual properties (IPs). As one original contribution, the article details the design of a digitally controlled oscillator (DCO) which is the core of the LCG architecture. This DCO was designed using a CMOS 65 nm technology. It produces at least 16 distinct frequencies from 117 MHz to 1 GHz and supports clock gating and glitch-free frequency changes. The DCO design is robust to process, voltage and temperature variations, takes 850.6 µm2 and dissipates up to 197 µW. The article also proposes an LCG controller to improve frequency accuracy for IPs which require more accurate timing. Designed in the same technology, the controller takes 2250 µm2 and consumes 130 µW in typical conditions, or 160 µW, under worst-case conditions.
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Acknowledgments
Authors acknowledge the support of CNPq under Grants 142263/2012-5, 401839/2013-3, 200147/2014-5, 202519/2014-7 and 310864/2011-9 and the support of CAPES.
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Heck, G., Heck, L.S., Moreira, M.T. et al. A new local clock generator for globally asynchronous locally synchronous MPSoCs. Analog Integr Circ Sig Process 89, 631–640 (2016). https://doi.org/10.1007/s10470-016-0827-9
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DOI: https://doi.org/10.1007/s10470-016-0827-9