Abstract
This paper proposes the use of alternative approximate adders for fully parallel energy-efficient complementary metal–oxide–semiconductor (CMOS) finite impulse response (FIR) filters design. The filters to be approximated are first optimized for low power by a state-of-the-art multiplier-less multiple constant multiplication algorithm. We further evaluate magnitude error and accuracy for different state-of-the-art approximate adder techniques plus the truncation of adders, and validate this with 16-bit audio signals histogram analysis. Once the approximation is performed for all the filters, we evaluate the signal-to-noise ratio (SNR) response for ten recorded audio signals. All precise and approximate filters benchmark cases with different SNR targets are synthesized and mapped onto a 45 nm CMOS PDK for full ASIC implementation. Energy-efficiency results show that our proposed approximate filters, subject to a 50 dB Signal to Noise + Distortion Ratio required floor, reduce on average the energy per filtered sample by up to 24.8 and 23.8 % for 100 and 10 MHz circuit operation, respectively.
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Park, J., Choi, J. H., & Roy, K. (2010). Dynamic bit-width adaptation in DCT: An approach to trade off image quality and computation energy. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(5), 787–793.
Markovic, D., Stojanovic, V., Nikolic, B., Horowitz, M. A., & Brodersen, R. W. (2004). Methods for true energy-performance optimization. IEEE Journal of Solid-State Circuits, 39(8), 1282–1293.
Han, J., & Orshansky, M. (2013). Approximate computing: An emerging paradigm for energy-efficient design. In Test Symposium (ETS), 2013 18th IEEE European (pp. 1–6). Avignon.
Kahng, B., & Kang, S. (2012). Accuracy-configurable adder for approximate arithmetic designs. In Proceedings of the 49th Annual Design Automation Conference (pp. 820–825). San Francisco.
Zhu, N., Goh, W. L., Zhang, W., Yeo, K. S., & Kong, K. S. (2010). Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(8), 1225–1229.
Gupta, V., Mohapatra, D., Park, S. P., Raghunathan, A., Roy, K. (2011). IMPACT: Imprecise adders for low-power approximate computing. In Proceedings of the 17th IEEE/ACM International Symposium on Low-Power Electronics and Design (pp. 409–414). Fukuoka.
Gupta, V., Mohapatra, D., Raghunathan, A., & Roy, K. (2013). Low-power digital signal processing using approximate adders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(1), 124–137.
Zhu, N., Goh, W. L., Wang, G., & Yeo, K. S. (2010). Enhanced low-power high-speed adder for error-tolerant application. In SoC Design Conference (ISOCC), 2010 International, Seoul.
Zhu, N., Goh, W. L., Yeo, K. S. (2009). An enhanced low-power high-speed adder for error-tolerant application. In ISIC’09, Proceedings of the 2009 12th International Symposium on Integrated Circuits (pp. 69–72). Singapore.
Anastasia, D., & Andreopoulos, Y. (2010). Software designs of image processing tasks with incremental refinement of computation. IEEE Transactions on Image Processing, 19(8), 2099–2114.
Andreopoulos, Y., & van der Schaar, M. (2008). Incremental refinement of computation for the discrete wavelet transform. IEEE Transactions on Signal Processing, 56(1), 140–157.
Aksoy, L., Gunes, E., & Flores, P. (2010). Search algorithms for the multiple constant multiplications problem: Exact and approximate. Elsevier Journal on Microprocessors and Microsystems, 34(5), 151–162.
Verma, K., Brisk, P., Ienne, P. (2008). Variable latency speculative addition: A new paradigm for arithmetic circuit design. In Proceedings of the Conference on Design, Automation and Test in Europe, Munich (pp. 1250–1255).
Tzanetakis, G., Cook, P. (2015). GTZAN dataset. http://marsyasweb.appspot.com/download/data_sets/. Accessed Nov 2, 2015.
Oklahoma State University. 45 nm FreePDK. http://vlsiarch.ecen.okstate.edu/flow/#. Accessed Nov 12, 2015.
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Soares, L.B., da Costa, E.A.C. & Bampi, S. Design of area and energy-efficient digital CMOS FIR filters with approximate adder circuits. Analog Integr Circ Sig Process 89, 99–109 (2016). https://doi.org/10.1007/s10470-016-0797-y
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DOI: https://doi.org/10.1007/s10470-016-0797-y