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Design and validation of a 10-bit current mode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS

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Abstract

A 10-bit 50 MS/s current-mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. Due to the absence of a switched capacitor feedback DAC, the value of the sampling capacitance can be chosen solely based on the kT/C noise required to achieve a certain performance. Then by designing the input Gm stage for a wide differential input voltage range, the resulting sampling capacitance value can be made significantly smaller compared to a conventional switched capacitor SAR ADC. Moreover, the presented design requires neither an external reference voltage to bias the Gm stage output nor a low-impedance DAC-reference voltage. To validate the proposed approach, a prototype 10-bit ADC is fabricated in a 90 nm TSMC CMOS process. Measured results of the ADC show an SFDR of 58.4 dB at 50 MS/s, while consuming 6 mW from a 1.2 /1.8 V supply.

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Authors and Affiliations

  1. Institute of Microelectronics, University of Ulm, Albert-Einstein Allee 43, Ulm, Germany

    Abdelrahman Elkafrawy, Jens Anders & Maurits Ortmanns

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  1. Abdelrahman Elkafrawy
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  2. Jens Anders
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  3. Maurits Ortmanns
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Correspondence to Abdelrahman Elkafrawy.

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Elkafrawy, A., Anders, J. & Ortmanns, M. Design and validation of a 10-bit current mode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS. Analog Integr Circ Sig Process 89, 283–295 (2016). https://doi.org/10.1007/s10470-016-0788-z

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