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Dc-gain enhanced folded cascode Op-amp using a new positive feedback method

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Abstract

In this paper, a novel operational amplifier is demonstrated which is established on the folded cascode Op-amp structure. A new technique of positive feedback is proposed to increase the open loop gain of Op-amp while not limiting its linearity. The proposed structure is simulated by HSPICE software using level 49 parameters (BSIM3V3) in a typical 0.18 µm CMOS technology. HSPICE simulation verifies the theoretical estimated improvements.

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References

  1. Dadashi, A., Sadrafshari, S, Hadidi, K, & Khoei, A. (2011). An enhanced folded cascode Op-Amp using positive feedback and bulk amplification in 0.35 μm CMOS process. Analog Integrated Circuits and Signal Processing, 67, 213–222.

    Article  Google Scholar 

  2. Hosticka, B. J. (1979). Improvement of the Gain of CMOS Amplifiers. IEEE Journal of Solid-State Circuits, 14, 1111–1114.

    Article  Google Scholar 

  3. Laber, C. A., & Gray, P. R. (1988). A positive-feedback transconductance amplifier with applications to high-frequency, high-Q CMOS switched-capacitor filters. IEEE Journal of Solid-State Circuits, 23(6), 1370–1378.

    Article  Google Scholar 

  4. Mahmoudi, A., Dadashi, A., Masoumi, S., & Kouzehkanan, M. K. H (2012). Dc-gain enhanced fast-settling triple folded cascode op-amp. Proceedings of 19th International Conference on Mixed Design of Integrated Circuits and Systems, Warsaw, pp. 235–238.

  5. Dadashi, A., Sadrafshari, Sh, & Hadidi, Kh. (2012). Fast-settling CMOS Op-Amp with improved DC-gain. Analog Integrated Circuits and Signal Processing, 70, 283–292.

    Article  Google Scholar 

  6. Hadidi, K., Sobhi, J., Hasankhaan, A., Muramatsu, D., & Matsumoto, T. (1998) A novel highly linear CMOS buffer. 1998 IEEE International Conference on Electronics, Circuits and Systems, pp. 369–371

  7. Eslami Farsani, M., & Ghaderi, N. (2015) Reduction of coupling capacitance, using a capacitor-transistor coupling circuit. International Conference on Electrical and Electronics Engineering, ELECO 2015, Bursa.

  8. Pourabdollah, M. (2016) A new gain-enhanced and slew-rate-enhanced folded-cascode op amp. Analog Integrated Circuits and Signal Processing, published online: 10 May 2016.

  9. Taherzadeh-Sani, M., & Hamoui, A. A. (2011). A 1-V process-insensitive current-scalable two- stage Op-amp with enhanced DC gain and settling behavior in 65-nm digital CMOS. IEEE Journal of Solid-State Circuits, 46(3), 660–668.

    Article  Google Scholar 

  10. Zuo, L., & Islam, S. K. (2013). Low-voltage bulk-driven operational amplifier with improved transconductance. IEEE Transactions on Circuits and Systems-I: Regular Papers, 60(8), 2084–2091.

    Article  Google Scholar 

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Correspondence to Noushin Ghaderi.

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Farsani, M.E., Ghaderi, N. Dc-gain enhanced folded cascode Op-amp using a new positive feedback method. Analog Integr Circ Sig Process 89, 771–779 (2016). https://doi.org/10.1007/s10470-016-0780-7

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  • DOI: https://doi.org/10.1007/s10470-016-0780-7

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