Skip to main content
SpringerLink
Log in

System-level post-optimization of Delta–Sigma modulators using finite difference stochastic approximation

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

Traditional methods for system-level design of Delta–Sigma (∆Σ) modulators typically assume linear modeling of the modulator, in which quantization noise is modeled as additive independent white noise. But it is well known that the ∆Σ modulator is a non-linear system and linear modeling is only an approximation. Also, circuit-level non-idealities, which may greatly change the modulator behavior, are typically neglected at system-level design. As a result, system-level modulator designs obtained from traditional methods may not be realistically optimal. This paper presents a system-level post-optimization method for ∆Σ modulators so that modulator designs initially obtained from traditional methods are post-optimized considering non-linear and non-ideal characteristics of ∆Σ modulators including both quantization noise and circuit-level non-idealities. The post-optimization algorithm is based on Finite Difference Stochastic Approximation due to the stochastic nature of modeling of some circuit-level non-idealities in system-level design. During the post-optimization run, each candidate design is simulated for performance measures and stability has always been a must constraint. Results on two ∆Σ modulators have shown that post-optimized modulator designs outperform the original designs from traditional methods.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  1. Veldhoven, R. (2003). A triple-mode continuous-time Delta–Sigma modulator with switched-capacitor feedback DAC for a GSMEDGE/CDMA2000/UMTS receiver. IEEE Journal of Solid-State Circuits, 38(12), 2069–2076.

    Article  Google Scholar 

  2. Norsworthy, S., Schreier, R., & Temes, G. (1996). Delta–sigma data converters: theory, design, and simulation. New York: IEEE Press.

    Book  Google Scholar 

  3. Schreier, R. (1993). An empirical study of high-order single-bit Delta–Sigma modulators. IEEE Transactions on Circuits and Systems II, 40(8), 461–466.

    Article  Google Scholar 

  4. Zhong, L., & Jha, N. (2005). Interconnect-aware low-power high-level synthesis. IEEE Transactions on CAD of Integrated Circuits and Systems, 24(3), 336–351.

    Article  Google Scholar 

  5. Hanchate, N., & Ranganathan, N. (2006). Post-layout gate sizing for interconnect delay and crosstalk noise optimization. In Proceedings of International Symposium on Quality Electronic Design

  6. Vancorenland, P., Plas, G., Steyaert, M., Gielen, G., & Sansen, W. (2001). A layout-aware synthesis methodology for RF circuits. In Proceedings of International Conference on Computer Aided Design.

  7. Bajdechi, O., Gielen, G., & Huijsing, J. (2004). Systematic design exploration of Delta–Sigma ADCs. IEEE Transactions Circuits and Systems I, 51(1), 86–95.

    Article  Google Scholar 

  8. Schreier, R. (2004). The Delta–Sigma Toolbox 6.0. http://www.mathworks.com/matlabcentral/fileexchange.

  9. Cherry, J. & Snelgrove, W. (2002). Continuous-time delta–sigma modulators for high-speed a/d conversion. Berlin: Kluwer Academic Publishers.

  10. Loeda, S., Martin, H., & Mulgrew, B. (2006). On the design of higher-performance wide-band continuous-time sigma-delta converters using numerical optimization. IEEE Transactions on Circuits and Systems I, 53(4), 802–810.

    Article  Google Scholar 

  11. Cherry, J., & Snelgrove, W. (1999). Clock jitter and quantizer metastability in continuous-time delta-sigma modulators. 676, 46(6), 661–676.

    Google Scholar 

  12. Malcovati, P., Brigati, S., Francesconi, F., Maloberti, F., Cusinato, P., & Baschirotto, A. (2003). Modeling sigma-delta modulator non-idealities in simulink. IEEE Transaction on Circuit and Systems I, 50(3), 352–364.

    Article  Google Scholar 

  13. Ruiz, J., Rosa, J., Medeiro, F., Fernandez, F., Rio, R., Perez, R., & Rodriguez, A. (2005). High-level synthesis of switched-capacitor, switched-current and continuous-time Sigma-Delta modulators using SIMULINK-based time-domain behavioral models. IEEE Transactions on Circuits and System I, 52(9), 1795–1810.

    Article  Google Scholar 

  14. Spall, J. (2003). Introduction to stochastic search and optimization: Estimation simulation and control. Hoboken: Wiley.

    Book  MATH  Google Scholar 

  15. Robbins, H., & Monro, S. (1951). A stochastic approximation method. Annals of Mathematical Statistics, 22(1951), 400–407.

    Article  MathSciNet  MATH  Google Scholar 

  16. MATLAB. (2012). MATLAB 2012Ra. The MathWorks Inc.

  17. Cadence. (2005). Analog Design Environment User Guide. The Cadence Inc.

  18. IBM. (2004). IBM CMRF7SF Model User Guide. IBM Corporation.

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Minnesota Duluth, Duluth, USA

    Hua Tang

Authors
  1. Hua Tang
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Hua Tang.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Tang, H. System-level post-optimization of Delta–Sigma modulators using finite difference stochastic approximation. Analog Integr Circ Sig Process 88, 31–42 (2016). https://doi.org/10.1007/s10470-016-0729-x

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-016-0729-x

Keywords

Search

Navigation