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A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS

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Abstract

This paper reviews the state-of-the-art of high switching frequency, integrated DC–DC converters and presents the main trade-offs and challenges emerging from this review. Various converter structures (1-phase buck, 2-phase buck, 2-phase coupled buck and 3-level converter) are then discussed and analyzed through simulation from a losses point-of-view. Considering the review, the architecture analysis and the technology model, 4 converters are designed for a given set of specifications: 3.3–1.2 V, 280 mA output current at high switching frequency (100–200 MHz) in 40 nm bulk CMOS. A cascode power stage is used in order to enhance power conversion efficiency, and 1-phase and 2-phase structures are designed. Post-layout simulation results are presented, showing an efficiency above 90 % for a 2-phase converter.

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Acknowledgments

This work is supported by the European Commission through the Seventh Framework Programme (FP7), under the Project Grant PowerSWIPE No. 318529.

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  1. Ampère Laboratory, University of Lyon, 21 Avenue Jean Capelle, 69621, Villeurbanne, France

    Florian Neveu, Bruno Allard & Christian Martin

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  1. Florian Neveu
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Correspondence to Florian Neveu.

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Neveu, F., Allard, B. & Martin, C. A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS. Analog Integr Circ Sig Process 87, 201–211 (2016). https://doi.org/10.1007/s10470-015-0683-z

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