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Design and analysis of folded cascode OTAs using Gm/Id methodology based on flicker noise reduction

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Abstract

In this paper, a new methodology for design of folded cascode (FC) and recycling folded cascode (RFC) OTAs based on 1/f noise reduction is presented. With a new formulation for input referred flicker noise based on Gm/Id characteristic in all operation regions significantly enhance of the noise performance is achieved. Also, this technique leads to the larger DC gain and gain-bandwidth, and phase margin degeneration. The amplifiers were simulated in the 0.18 μm CMOS technology and the simulation results confirm the theoretical analyses. Proposed design methodology exhibits 50 % reduction of input voltage noise @ 1 Hz for RFC compared to the FC amplifier, without increasing the power consumption and silicon area.

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Authors and Affiliations

  1. Microelectronic Laboratory, Shahid Beheshti University, G.C., Tehran, Iran

    Meysam Akbari

  2. Departement of Electrical and Copmuter Engineering, Shahid Beheshti University, G.C., Tehran, Iran

    Omid Hashemipour

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  1. Meysam Akbari
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  2. Omid Hashemipour
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Correspondence to Meysam Akbari.

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Akbari, M., Hashemipour, O. Design and analysis of folded cascode OTAs using Gm/Id methodology based on flicker noise reduction. Analog Integr Circ Sig Process 83, 343–352 (2015). https://doi.org/10.1007/s10470-015-0535-x

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  • DOI: https://doi.org/10.1007/s10470-015-0535-x

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