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A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS

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Abstract

This paper presents a fully integrated 40-GHz transceiver designed for 2 Gbit/s short-range chip-to-chip communication link. The proposed architecture includes both the transmitter and the receiver and is optimized for on–off-keying modulation scheme. The transceiver design includes two variants, which can drive either a planar on-chip antenna or wire-bonded off-chip antenna. The performance comparison of these is given in the paper. A compact and energy-efficient technique has been adopted by directly modulating the oscillator in the transmitter. The receiver uses a self-mixing topology followed by transimpedance amplifier and a limiter chain. The detailed circuit descriptions as well as design trade-offs with simulation results in 65 nm CMOS are given. In addition, an example design modification to extend the modulation to 4-level amplitude shift keying is presented.

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Acknowledgments

The authors would like to thank Saska Lindfors, Kari Stadius and Mikko Englund for their technical assistance. This work has been financially supported by Academy of Finland.

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Authors and Affiliations

  1. Department of Micro and Nanosciences, Aalto University, Espoo, Finland

    Tero Tikka, Olli Viitala & Jussi Ryynänen

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  1. Tero Tikka
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  2. Olli Viitala
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  3. Jussi Ryynänen
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Correspondence to Tero Tikka.

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Tikka, T., Viitala, O. & Ryynänen, J. A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS. Analog Integr Circ Sig Process 83, 23–33 (2015). https://doi.org/10.1007/s10470-015-0501-7

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  • DOI: https://doi.org/10.1007/s10470-015-0501-7

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