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A broad-band V-band power amplifier using a reduced access-resistance transistor layout in 65-nm CMOS

  • Mixed Signal Letter
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Abstract

To improve millimeter-wave amplifier performance, we propose a transistor layout that reduces the gate access resistance. The proposed layout trades overlap capacitance for reduced gate access resistance, as shown by transistor parameter extraction. The proposed transistor layout improves the maximum available power gain by 1.5 dB at 67 GHz. The extrapolated maximum frequency of oscillation (f max) also increases by 23 % from 91.3 to 112.5 GHz. Using the improved transistor layout, we design a V-band power amplifier that has enhanced performance. The power amplifier fabricated using the proposed transistor achieves 15.1 dB of small-signal gain, 16.5 GHz of 3-dB bandwidth, and an output power of 7.8 dBm at 61.5 GHz. Compared to an amplifier using conventional layout, the small-signal gain is improved by 3.7 dB and the output power is increased by 3 dBm at 61.5 GHz.

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Acknowledgments

This work was supported by the Mid-Career Researcher Program through the National Research Foundation of Korea (no. 2012-001327). The CAD tools used for this design were supported by the IC Design Education Center (IDEC), Korea.

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Authors and Affiliations

  1. School of Electronics and Information, Kyung Hee University, Suwon, 446-701, Korea

    Seung-Yeon Kim, Nguyen Xuan Hieu & Jong-Wook Lee

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  1. Seung-Yeon Kim
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  2. Nguyen Xuan Hieu
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  3. Jong-Wook Lee
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Correspondence to Jong-Wook Lee.

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Kim, SY., Hieu, N.X. & Lee, JW. A broad-band V-band power amplifier using a reduced access-resistance transistor layout in 65-nm CMOS. Analog Integr Circ Sig Process 82, 487–493 (2015). https://doi.org/10.1007/s10470-014-0478-7

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  • DOI: https://doi.org/10.1007/s10470-014-0478-7

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