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An error-feedback noise-shaping SAR ADC in 90 nm CMOS

  • Mixed Signal Letter
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Abstract

In this paper, a new structure is proposed to utilize the noise-shaping in a charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC). The proposed ADC is based on the error-feedback structure and it does not require any extra capacitor compared to the main SAR ADC and just by employing an operational transconductance amplifier (OTA), a first-order noise-shaping is provided. The closed-loop configuration of the OTA is similar to the flip-around scheme in which the dummy capacitor also acts as the sampling capacitor. In this configuration, the quantization noise of the ADC is sampled and transferred via the dummy capacitor without any charge sharing or capacitor interleaving, and so, the capacitors mismatch is alleviated in the feedback path. The proposed ADC is realized by employing a few number of capacitors and switches compared to the conventional SAR ADC. As a design example, the proposed noise-shaping SAR ADC is simulated in a 90 nm CMOS technology by employing a 3-bit SAR ADC. Simulation results with Spectre-RF shows 11.1-bit effective resolution in 1 MHz input bandwidth and 128 MHz sampling rate while consuming 208 μW power. The achieved figure of merit is 46.4 fJ/conv-step.

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Author information

Authors and Affiliations

  1. Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology (Tehran Polytechnic), 424 Hafez Ave., Tehran, Iran

    Mohsen Shahghasemi, Reza Inanlou & Mohammad Yavari

Authors
  1. Mohsen Shahghasemi
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  2. Reza Inanlou
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  3. Mohammad Yavari
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Corresponding author

Correspondence to Mohammad Yavari.

Appendix

Appendix

In order to evaluate the decimation filters power and area overhead in the proposed ADC, this appendix is provided. The required decimation filters for the designed prototype are modeled in MATLAB and Simulink. As shown in Fig. 7, a multi-stage configuration for decimation filters is utilized which is more power efficient than a single-stage one [17]. A second-order Sinc filter with a 16 down-sampling ratio is used since the noise-shaping order in the proposed ADC is one. Two halfband filters are used to reduce the rate of the ADC output to the Nyquist rate. The first halfband filter is a 11th order digital filter which has seven taps. The order of the second halfband filter is 15th with nine taps. By using this decimation filter, the ADC maximum SQNR drops from the ideal 70.5 dB to about 69.9 dB which is degraded about 0.6 dB. The resulting output spectrum of the total ADC including the decimation filters is shown in Fig. 8.

Fig. 7
figure 7

Three-stage decimation filter

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Fig. 8
figure 8

Nyquist rate output spectrum of the designed ADC resulting from the system level simulations

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To estimate the decimation filters power consumption and area, the design presented in [18] is utilized. In [18], OSR = 64, the input rate of the decimation filter is 3.072 MHz, a fourth-order Sinc filter is used with 20-bit resolution in filter taps. Moreover, the first halfband filter is a 10th order filter with 24-bit resolution in filter taps. The above-mentioned decimation filter has been fabricated in a 0.18 μm CMOS technology with 1.8 V power supply. To estimate the power consumption and the area according to this filter, some scaling coefficients must be used such as the following. The voltage reduction coefficient is 1/1.8. This coefficient has no effect on the area but it changes the power consumption by its square. The technology scaling coefficient is 0.09/0.18. This coefficient changes both the area and dynamic power by its square. The resolution of the block (number of bits in the block) coefficient changes the power consumption and the area directly. The frequency scaling coefficient does not change the area but it reduces the dynamic power directly. Finally, the hardware changes coefficient (such as the filter order or number of taps) directly affects both the power consumption and area. Although we consider all power sources as dynamic and this makes the estimation highfalutin, but an overestimation coefficient with a quantity of 1.25 is also used to provide a conservative estimation.

The power consumption and area of the second-order Sinc filter in Fig. 7 are estimated as, respectively:

$$P_{Sinc2} = \mathop {\left( {\frac{1}{1.8}} \right)^{2}}\limits_{Voltage}.\mathop {\left( {\frac{0.09}{0.18}} \right)^{2}}\limits_{{Technology}}.\mathop {\left( \frac{13}{20} \right)}\limits_{No\,.\,of\,bits} .\mathop {\left( {\frac{128}{3.072}} \right)}\limits_{Frequency} .\mathop {\left( \frac{1}{2} \right)}\limits_{Hardware} \times 46.4 \times \mathop {1.25}\limits_{Overestimation} = 60.60\,\mu W$$
(11)
$$A_{Sinc2} = \mathop {\left( {\frac{0.09}{0.18}} \right)^{2}}\limits_{{Technology}}.\mathop {\left( \frac{13}{20} \right)}\limits_{No\,.\,of\,bits} .\mathop {\left( \frac{1}{2} \right)}\limits_{Hardware} \times 29985 \times \mathop {1.25}\limits_{Overestimation} = 3,066\mu m^{2}$$
(12)

The power consumption and area of the first halfband filter are estimated as:

$$P_{HBF1} = \mathop {\left( {\frac{1}{1.8}} \right)^{2}}\limits_{Voltage}.\mathop {\left( {\frac{0.09}{0.18}} \right)^{2}}\limits_{{Technology}}.\mathop {\left( \frac{14}{24} \right)}\limits_{No\,.\,of\,bits} .\mathop {\left( \frac{4000}{96} \right)}\limits_{Frequency} .\mathop {\left( \frac{7}{5} \right)}\limits_{No.\,of\,taps} \times 5.9 \times \mathop {1.25}\limits_{Overestimation} = 19.38\,\mu W$$
(13)
$$A_{HBF1} = \mathop {\left( {\frac{0.09}{0.18}} \right)^{2}}\limits_{{Technology}}.\mathop {\left( \frac{14}{24} \right)}\limits_{No\,.\,of\,bits} .\mathop {\left( \frac{7}{5} \right)}\limits_{Hardware} \times 41941 \times \mathop {1.25}\limits_{Overestimation} = 10,703\mu m^{2}$$
(14)

Since the number of coefficients of the second halfband filter is not specified in [18], its power consumption and area are calculated according to the first halfband filter as:

$$P_{HBF2} = \mathop {\left( {\frac{1}{1.8}} \right)^{2}}\limits_{Voltage}.\mathop {\left( {\frac{0.09}{0.18}} \right)^{2}}\limits_{{Technology}} .\mathop {\left( \frac{15}{24} \right)}\limits_{No\,.\,of\,bits} .\mathop {\left( \frac{2000}{96} \right)}\limits_{Frequency} .\mathop {\left( \frac{9}{5} \right)}\limits_{No.\,of\,taps} \times 5.9 \times \mathop {1.25}\limits_{Overestimation} = 13.34\,\mu W$$
(15)
$$A_{HBF2} = \mathop {\left( {\frac{0.09}{0.18}} \right)^{2}}\limits_{{Technology}}.\mathop {\left( \frac{15}{24} \right)}\limits_{No\,.\,of\,bits} .\mathop {\left( \frac{9}{5} \right)}\limits_{Hardware} \times 41941 \times \mathop {1.25}\limits_{Overestimation} = 14,745\mu m^{2}$$
(16)

Consequently, for the targeted design example, the power consumption in the required decimation filters is approximately 93.3 μW and its area is about 28,514 μm2.

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Shahghasemi, M., Inanlou, R. & Yavari, M. An error-feedback noise-shaping SAR ADC in 90 nm CMOS. Analog Integr Circ Sig Process 81, 805–814 (2014). https://doi.org/10.1007/s10470-014-0434-6

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