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A 360 fJ/conversion-step, 14-bit, 100 MS/s, digitally background calibrated pipelined ADC in 130-nm CMOS

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Abstract

This paper describes a 14-bit digitally background calibrated pipeline analog-to-digital converter (ADC) implemented in a mainstream 130-nm CMOS technology. The proposed calibration technique linearizes the digital output to correct for errors resulting from capacitor mismatch, finite amplifier gain, voltage reference errors and differential offsets. The software-based calibration technique requires quite modest digital resources and its estimated dynamic power is under 1 % of the ADC power consumption. After calibration, the 14-bit ADC achieves a measured peak Signal-to-Noise-plus-Distortion-Ratio of 71.1 dB at 100 MS/s sampling rate. The worst-case integral nonlinearity is improved from 32.9 down to 4 Least-Significant-Bits after calibration. The chip occupies an active area of 1.25 mm2 and the core ADC (S/H+analog+digital power) consumes 105 mW. The Figure-of-Merit is 360 fJ per conversion-step.

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Authors and Affiliations

  1. Texas A&M University, College Station, TX, 77843, USA

    A. Larsson, J. Silva-Martinez & E. G. Soenen

  2. Taiwan Semiconductor Manufacturing Company, Austin Design Center, Austin, TX, USA

    E. G. Soenen

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  1. A. Larsson
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  2. J. Silva-Martinez
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  3. E. G. Soenen
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Correspondence to A. Larsson.

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Larsson, A., Silva-Martinez, J. & Soenen, E.G. A 360 fJ/conversion-step, 14-bit, 100 MS/s, digitally background calibrated pipelined ADC in 130-nm CMOS. Analog Integr Circ Sig Process 81, 153–164 (2014). https://doi.org/10.1007/s10470-014-0376-z

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  • DOI: https://doi.org/10.1007/s10470-014-0376-z

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