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Design of highly integrated power management unit with dual DVS-enabled regulators

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Abstract

A highly integrated power management unit (PMU) with dual DVS-enabled regulators is proposed in this paper. The PMU provides four buck regulators and two low dropout regulators, in which there are two DVS-enabled buck regulators. The output voltages can be optimized separately in the applications with two adaptive voltage domains. The PMU with dual DVS-enabled regulators provides high efficiency and convenient solution for portable devices. The voltage and current references are distributed by considering substrate noise from switching regulators. Interleaving operation of switching regulators minimizes input current ripple. Floating ground is generated in the control block of switching regulators by voltage buffer to further improve the negative power supply rejection (PSR−). The PMU is designed and fabricated with 0.13 μm CMOS process and occupies 5.29 mm2 active silicon area. Experimental results show that the PMU provides good isolation between channels and the DVS speeds for 250 mA ILoad are 63.6 and 45.5 μs/V when up-tracking and down-tracking, respectively. The proposed PMU can be embedded in low power SoCs, facilitating the DVFS scheme for multiple voltage domains.

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Acknowledgments

This work was supported in part by the Project Grant 51308020305 and NSFC Project Grant 61274027.

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Authors and Affiliations

  1. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, People’s Republic of China

    Shaowei Zhen, Ping Luo & Bo Zhang

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  1. Shaowei Zhen
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  2. Ping Luo
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  3. Bo Zhang
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Correspondence to Shaowei Zhen.

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Zhen, S., Luo, P. & Zhang, B. Design of highly integrated power management unit with dual DVS-enabled regulators. Analog Integr Circ Sig Process 80, 209–220 (2014). https://doi.org/10.1007/s10470-014-0313-1

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  • DOI: https://doi.org/10.1007/s10470-014-0313-1

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