Skip to main content
SpringerLink
Log in

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

  • Mixed Signal Letter
  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

References

  1. Chatterjee, S., et al. (2005). 0.5-V analog circuit techniques and their application in OTA and filter design. IEEE Journal of Solid-State Circuits, 40(12), 2373–2387.

    Article  Google Scholar 

  2. Goll, B., & Zimmermann, H. (2009). A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Transactions on Circuits and Systems II, 56(11), 810–814.

    Article  Google Scholar 

  3. Lin, Y., Doris, K., et al. (2012). A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS. In Proceedings of IEEE international symposium on circuits and systems (ISCAS) (pp. 2737–2740).

  4. Kandala, M., & Wang, H. (2012). A 0.5 V high-speed comparator with rail-to-rail input range. Analog Integrated Circuits and Signal Processing, 73(1), 415–421.

    Article  Google Scholar 

  5. Maymandi-Nejad, M., & Sachdev, M. (2003). 1-bit quantiser with rail to rail input range for sub-1V ΔΣ modulators. Electronics Letters, 39(12), 894–895.

    Article  Google Scholar 

  6. Wang, J. (2008). Design of a 0.5 V op-amp based on CMOS inverter using floating voltage sources. IEICE Transactions on Electronics, E91-C(8), 1375–1378.

    Article  Google Scholar 

  7. Nikoozadeh, A., & Murmann, B. (2006). An analysis of latch comparator offset due to load capacitor mismatch. IEEE Transactions on Circuits and Systems II, 53(12), 1398–1402.

    Article  Google Scholar 

  8. Lee, M. J. E., et al. (2000). Low-power area-efficient high-speed I/O circuit techniques. IEEE Journal of Solid-State Circuits, 35(11), 1591–1599.

    Article  Google Scholar 

  9. Sadeghipour, K. D. (2011). An improved low offset latch comparator for high-speed ADCs. Analog Integrated Circuits and Signal Processing, 66(2), 205–212.

    Article  Google Scholar 

  10. Miyahara, M., et al. (2008). A low-noise self-calibrating dynamic comparator for high-speed ADCs. In IEEE Asian solid-state circuits conference proceeding, Japan, pp. 269–272.

Download references

Author information

Authors and Affiliations

  1. Anasystem Azerbaijan, East Azerbaijan Science and Technology Park, Tabriz, Iran

    Meysam Mohammadi Khanghah

  2. University of Tabriz, Tabriz, Iran

    Khosrov Dabbagh Sadeghipour

Authors
  1. Meysam Mohammadi Khanghah
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Khosrov Dabbagh Sadeghipour
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Meysam Mohammadi Khanghah.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Mohammadi Khanghah, M., Sadeghipour, K.D. A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process. Analog Integr Circ Sig Process 79, 161–169 (2014). https://doi.org/10.1007/s10470-013-0239-z

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-013-0239-z

Keywords

Search

Navigation