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A reference-free 7-bit 500 MS/s pipeline ADC using current-mode reference shifting and quantizers with built-in thresholds

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Abstract

The pursuit for energy and area efficient circuits has become greater than ever. Low power and small area integrated circuits are in high demand today. Reference voltage circuitry for analog-to-digital conversion comprises 20–30 % of the overall power and area of the ADC. To this end, a fully differential 1.5-bit multiplying digital-to-analog converter (MDAC) precluding reference voltages, that can be employed in MDAC-based ADCs, is presented. Reference shifting is performed in current-mode and the gain of two is obtained by associating charged capacitors in series in the opamp’s feedback loop, achieving a unity feedback factor. Theoretical analyses of various nonideal effects of the reference shifting and gain of two are presented and confirmed with electrical level simulations. Furthermore, to avoid reference voltages in the local quantizers, an architecture with built-in thresholds is used. A proof of concept 1.5-bit/stage 7-bit 500 MS/s pipeline ADC is designed using the proposed MDAC in a standard digital 0.13 μm CMOS technology. The ADC achieves a peak SNDR and SFDR of 36.1 and 48.7 dB, respectively, while dissipating 12.7 mW from a single 1.2 V supply voltage, and it does not require external reference circuitry.

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Notes

  1. MDAC-based ADCs are composed of the multi-step flash, the multi-stage algorithmic, and the pipeline architectures.

  2. In [9] it is demonstrated that reference voltage circuits can have 1-bit lower accuracy than the resolution of the ADC.

  3. The capacitor mismatch-insensitivity advantage is validated theoretically here, but not emphasized in the prototype ADC because the objective of this paper is to demonstrate how the proposed MDAC solves system-level issues.

  4. If I P and I N are not exactly matched, a current error (I e ) arises and results in an additive term appearing at the end of (3). It only affects the capacitor mismatch error (5), depending mainly on an I e /I REF term. For values of I e /I REF up to 20 %, I e may be neglected. Small I e is easily achieved using nonminimum transistor lengths.

  5. This is true assuming an equal C L for both the proposed and conventional MDACs. However, in a pipeline ADC employing the proposed MDAC in all stages, the β enhancement factor reduces to 2, because of the extra sampling capacitor, C 3j .

  6. The model of the opamp used in these simulations has A 0 = 106 dB, GBW = 3.2 GHz, and a load capacitance, C L , of 2 pF is considered.

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Acknowledgments

This work was supported in part by the Portuguese Foundation for Science and Technology under projects IMPACT (PTDC/EEA-ELC/101421/2008), OBiS FRET (PTDC/CTM/099511/2008), and Ph.D. grants BD/41524/2007 and BD/62568/2009.

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Authors and Affiliations

  1. Department of Electrical Engineering, Faculty of Sciences and Technology, Centre of Technology and Systems (UNINOVA-CTS), Universidade Nova de Lisboa, 2829-516, Caparica, Portugal

    Michael Figueiredo, Edinei Santin, João Goes & Nuno Paulino

  2. S3-Group, Madan Parque, Rua dos Inventores, 2825-182, Caparica, Portugal

    João Goes & Nuno Paulino

  3. Departamento de Física, The Centro de Física da Matéria Condensada, Faculdade de Ciências da, Universidade de Lisboa, Edifício C8, 1749-016, Lisbon, Portugal

    Guiomar Evans

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  1. Michael Figueiredo
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Correspondence to Michael Figueiredo.

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Figueiredo, M., Santin, E., Goes, J. et al. A reference-free 7-bit 500 MS/s pipeline ADC using current-mode reference shifting and quantizers with built-in thresholds. Analog Integr Circ Sig Process 75, 53–65 (2013). https://doi.org/10.1007/s10470-013-0030-1

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