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Design, implementation and measurement of a 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS

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Abstract

A novel mm-wave phase modulating transmit architecture, capable of achieving data rates as high as 10 Gb/s is presented at 120 GHz. The circuit operates at a frequency of 120 GHz. The modulator consists of a differential branchline coupler and a high speed 4-to-1 analog multiplexer with direct digital input. Both a QPSK as well as a 8QAM constellation are supported. To achieve high output power, a 9-stage power amplifier is designed and connected to the multiplexer output. The complete chip is integrated in a 65 nm low power CMOS technology. Capacitive neutralization is used to achieve high gain and good stability for the MOS devices. Also, various differential transmission line topologies are investigated to achieve high performance in terms of loss and area consumption.

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References

  1. Emami, S., Wiser, R. F., Ali, E., Forbes, M. G., Gordon, M. Q., Guan, X., Lo, S., McElwee, P. T, Parker, J., Tani, J. R., Gilbert, J. M., Doan, C. H. (2011). A 60GHz CMOS phased-array transceiver pair for multi-Gb/s wireless communications. International Solid-State Circuits Conference, ISSCC 2011, IEEE, pp. 164–165,

  2. Siligaris, A., Richard, O., Martineau, B., Mounet, C., Chaix, F., Ferragut, R., Dehos, C., Lanteri, J., Dussopt, L., Yamamoto, S. D., Pilard, R., Busson, P., Cathelin, A., Belot, D., Vincent, P. (2011). A 65nm CMOS fully integrated transceiver module for 60GHz wireless HD applications. International Solid-State Circuits Conference, ISSCC 2011, IEEE, pp. 162–163.

  3. Niknejad, A. M., Doan, C. H., Emami, S., Sobel, D., Brodersen, R. W. (2004). "60 GHz CMOS radio for Gb/s wireless LAN," Radio Frequency Integrated Circuits Symposium, RFIC 2004, IEEE, pp. 225–228.

  4. Okada, K., Matsushita, K., Bunsen, K., Murakami, R., Musa, A., Sato, T., Asada, H., Takayama, N., Li, Ning, Ito, S., Chaivipas, W., Minami, R., Matsuzawa, A. (2011). A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. International Solid-State Circuits Conference, ISSCC 2011, IEEE, pp. 160–161.

  5. Takahashi, H., Kosugi, T., Hirata, A., Murata, K., Kukutsu, N. (2010). 10-Gbit/s quadrature phase-shift-keying modulator and demodulator for 120-GHz-band wireless links. Transactions on Microwave Theory and techniques, TMTT 2010, IEEE 58(12), 4072–4078.

    Google Scholar 

  6. Takahashi, H., Kosugi, T., Hirata, A., Murata, K., Kukutsu, N. (2011). 10-Gbit/s BPSK modulator and demodulator for a 120-GHz-band wireless link. Transactions on Microwave Theory and techniques TMTT 2011, IEEE 59(5), 1361–1368.

    Article  Google Scholar 

  7. Niknejad, A. M., Emami, S., Heydari, B., Bohsali, M., Adabi, E. (2007). Nanoscale CMOS for mm-wave applications. Compound Semiconductor Integrated Circuit Symposium, CSIC 2007, IEEE, pp. 1–4.

  8. Deferm, N., Reynaert, P. (2011). A 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS. International Solid-State Circuits Conference, ISSCC 2011, IEEE, pp. 290–291.

  9. Deferm, N., Reynaert, P., (2010). A 100 GHz transformer-coupled fully differential amplifier in 90 nm CMOS.Radio Frequency Integrated Circuits Symposium, RFIC 2010, IEEE, pp. 359–362.

  10. Voinigescu, S. P., Nicolson, S. T., Khanpour, M., Tang, K. K. W., Yau, K. H. K., Seyedfathi, N., Timonov, A., Nachman, A., Eleftheriades, G., Schvan, P., Yang, M. T. (2007) CMOS SOCs at 100 GHz: System architectures, device characterization, and IC design examples. International Symposium on Circuits and Systems, ISCAS 2007, IEEE, pp. 1971–1974.

  11. Chan, W. L., Long, J. R. (2010). A 58–65 GHz neutralized CMOS power amplifier with PAE above 10 % at 1-V Supply. Journal of Solid-State Circuits, JSSC 2010, IEEE, 45(3):554–564

    Article  Google Scholar 

  12. LaRocca, T., Liu, J. Y. C., Chang, Mau-Chung, F. M. C. (2009). 60 GHz CMOS amplifiers using transformer-coupling and artificial dielectric differential transmission lines for compact design. Journal of Solid-State Circuits, JSSC 2010, IEEE, 44(5), 1425–1435.

    Article  Google Scholar 

  13. “Transmission line loss,” Internet: http://www.microwaves101.com/encyclopedia/transmission_loss.cfm, November 2010, [October 2012].

  14. Kuo, C.-J., Chen, A. Y.-K., Lee, C.-M., Luo, C.-H. (2011). Miniature 60 GHz slow-wave CPW branch-line coupler using 90 nm digital CMOS process. Electronic Letters, EL 2011, IEEE, 47(16), 924–925.

    Article  Google Scholar 

  15. Haroun, I., Wight, J., Plett, C., Fathy, A., Da-Chiang, C. (2011). Experimental analysis of a 60 GHz compact EC-CPW branch-line coupler for mm-Wave CMOS radios. Microwave and Wireless Components Letters, LMWC 2011, IEEE, 20(4), 211–213

    Article  Google Scholar 

  16. Chowdhury, D., Reynaert, P., Niknejad, A. M. (2009). Design considerations for 60 GHz transformer-coupled CMOS power amplifiers. Journal of Solid State Circuits, JSSC 2009, IEEE, 44(10), 2733–2744.

    Article  Google Scholar 

  17. Kawasaki, K., Akiyama, Y., Komori, K., Uno, M., Takeuchi, H., Itagaki, T., Hino, Y., Kawasaki, Y., Ito, K., Hajimiri, A. (2010). A millimeter-wave intra-connect solution. Journal of Solid-State Circuits, JSSC 2010, IEEE, 45(13), 2655–2666.

    Article  Google Scholar 

  18. Sandstrm, D., Varonen, M., Krkkinen, M., Halonen, K. A. I. (2010). A W-band 65 nm CMOS transmitter front-end with 8 GHz IF bandwidth and 20 dB IR-ratio. International Solid-State Circuits Conference, ISSCC 2010, IEEE, pp. 418–419.

  19. Kawano, Y., Suzuki, T., Sato, M., Hirose, T., Joshin, K. (2009). A 77 GHz transceiver in 90 nm CMOS. International Solid-State Circuits Conference, ISSCC 2009, IEEE, pp. 310–311.

  20. Marcu, C., Chowdhury, D., Thakker, C., Kong, L., Tabesh, M., Park, J., Wang, Y., Afshar, B., Gupta, A., Arbabian, A., Gambini, S., Zamani, R., Niknejad, A. M., Alon, E. (2009) A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry. International Solid-State Circuits Conference, ISSCC 2009, IEEE, pp. 314–315.

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Acknowledgment

This research is partly supported by the ERC Advanced Grant 227680, the CHIPS K.U.Leuven Program Financing (Circuit design for smart and high-performance electronic systems) and GOA 09.003 Concerted Research Activity (Design of RF-CMOS integrated circuits in the 30–300 GHz frequency band). Furthermore, the authors would like to thank NXP research Eindhoven to support this work. The authors also thank the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT Vlaanderen). Rhode & Schwarz is also acknowledged for supporting the measurement setup.

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Correspondence to Noël Deferm.

Appendix

Appendix

Tables 5, 6 and 7 respectively give an overview of the impact of process corners, temperature and supply variations on the input and output impedance of a neutralized pseudo differential pair.

Table 5 Impact of process variation on input and output impedance of the neutralized pseudo differential pair
Table 6 Impact of temperature variation on input and output impedance of the neutralized pseudo differential pair
Table 7 Impact of supply voltage variation on input and output impedance of the neutralized pseudo differential pair

Impact of adding a center line in a differential transmission line on Zc, β and α are respectively depicted in Figs. 45, 46 and 47.

Fig. 45
figure 45

Impact of the center line on Zc

Fig. 46
figure 46

Impact of the center line on β

Fig. 47
figure 47

Impact of the center line on α

Equations that describe the G and S input impedance of the GSG probepad with balanced load.

$$ Z_G = \left(s \cdot \frac{L_{in}}{2} + \frac{1}{\frac{1}{\frac{R_{subpad}}{2} + \frac{1}{s \cdot 2 \cdot C_{pad}}} + \frac{1}{R_{subTL} + \frac{1}{s \cdot C_{TLG}}} + 2 \cdot s \cdot C_{TL} + \frac{1}{s \cdot L_{TL} + \frac{1}{2 \cdot s \cdot C_{TL}}}} \right)// (R_{subprobe} + \frac{1}{s \cdot C_{probe}}) $$
(A-1)
$$ Z_S = s \cdot L_{in} + \frac{1}{\frac{1}{R_{subpad} + \frac{1}{s \cdot C_{pad}}} + \frac{1}{R_{subTL} + \frac{1}{s \cdot C_{TLG}}} + 2 \cdot s \cdot C_{TL} + \frac{1}{s \cdot L_{TL} + \frac{1}{2 \cdot s \cdot C_{TL}}}} $$
(A-2)

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Deferm, N., Reynaert, P. Design, implementation and measurement of a 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS. Analog Integr Circ Sig Process 75, 1–19 (2013). https://doi.org/10.1007/s10470-013-0027-9

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