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A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback

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Abstract

The performance of continuous time delta-sigma modulators is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback DACs. To mitigate that effect, a dual switched-capacitor-resistor feedback DAC technique is proposed. The architecture has the additional benefit of reducing the typically high switched-capacitor-resistor DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. The feedback technique has been implemented with a third order, 3-bit delta-sigma modulator for a low power radio receiver, in a 65 nm CMOS process, where it occupies an area of 0.17 mm2. It achieves an SNDR of 70 dB over a 125 kHz bandwidth with an oversampling ratio of 16. The power consumption is 380 μW from a 900 mV supply.

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Correspondence to Dejan Radjen.

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Radjen, D., Andreani, P., Anderson, M. et al. A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback. Analog Integr Circ Sig Process 74, 21–31 (2013). https://doi.org/10.1007/s10470-012-9960-2

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  • DOI: https://doi.org/10.1007/s10470-012-9960-2

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