Abstract
Currently, most integrated circuits have higher density of transistors on the small physical area, reduced power consumption and greater performance. An important factor that has contributed for this is the representation of logic functions with a reduced number of transistors. While the generation of a series–parallel network can be straightforward once a minimized Boolean expression is available, this may not be an optimum solution. This paper proposes a graph-based solution for minimizing the number of transistors that compose a network by edges sharing. The algorithm starts from a sum-of-products expression and can achieve non-series-parallel arrangements. The Wheatstone bridge arrangements contribute for the transistor count reduction. Experimental results demonstrate the efficiency of the approach when comparing to traditional factorization algorithms implemented in the SIS software. When applying to the set of four input p-class logic functions, the proposed method presents advantages if compared to the good-factor algorithm.
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Possani, V.N., de Souza, R.S., Domingues, J.S. et al. Optimizing transistor networks using a graph-based technique. Analog Integr Circ Sig Process 73, 841–850 (2012). https://doi.org/10.1007/s10470-012-9874-z
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DOI: https://doi.org/10.1007/s10470-012-9874-z