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FPGA-implementation of dynamic time delay neural network for power amplifier behavioral modeling

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Abstract

In this paper, we propose new architectures for FPGA-implementation of a dynamic neural network power amplifier behavioral modeling. The real-valued time-delay neural network (RVTDNN) and the backpropagation (BP) learning algorithm were implemented on FPGA using Xilinx system generator for DSP and the Virtex-6 FPGA ML605 evaluation kit. Different RVTDNN architectures are proposed for various values of the number of hidden neurons, the activation function resolution, and the fixed-point data format. These architectures are evaluated and compared in terms of modeling performances and resource utilization using 16-QAM modulated test signal.

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Authors and Affiliations

  1. Department of Engineering, Université du Québec à Rimouski, 300, allée des Ursulines, Rimouski, QC, G5L 3A1, Canada

    Mohammed Bahoura & Chan-Wang Park

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  1. Mohammed Bahoura
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  2. Chan-Wang Park
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Correspondence to Mohammed Bahoura.

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Bahoura, M., Park, CW. FPGA-implementation of dynamic time delay neural network for power amplifier behavioral modeling. Analog Integr Circ Sig Process 73, 819–828 (2012). https://doi.org/10.1007/s10470-012-9857-0

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  • DOI: https://doi.org/10.1007/s10470-012-9857-0

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